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The end of Dennard scaling has led to an increase in demand for energy-efficient custom hardware accelerators, but current hardware design is slow and laborious, partly because each iteration of the compile-run-debug cycle can take hours or even days with existing simulation and emulation platforms. Cyclist is a new emulation platform designed specifically to shorten the total compile-run-debug cycle...
When learning different control related concepts and methods, simulation is often used as a training tool; but, it does not have some real time characteristics of implementation like dealing with coding and PC resources, supervision, and communications. In some cases, implementation cannot be carried away, since it involves hardware design and is expensive. The proposed solution in this paper involves...
In this paper, we propose a high accuracy multi-chain time interval measurement (TIM) technique by employing the dedicated carry chain of FPGA. According to the principle of delay chain time to digital converter (TDC), the proposed method is realized by connecting the selectors inside the slices. The resolution of the delay chain method is limited by the time delay of one delay unit. To break through...
A standard priority-queuing system is capable of arranging packets with different traffic classes to guarantee a relatively low latency for the high priority traffic. However, in practical cases, severe delay may be caused by starting a large, low-priority frame ahead of a time-critical frame. In this paper, interspersed express traffic is evaluated, which enables preemption of non-time-critical transmission,...
In this article we propose the implementation of different RNS moduli sets on FPGA. We also reviewed methods for calculation of remainder of division by modules of special form. In addition, the application of logical sharing schemes with effective distributing of FPGA resources is presented in the paper. We modified the algorithm of residue calculation by using distributed arithmetic's methods and...
Paper considers the problem of asynchronous wideband signal detection. This problem is particularly acute for pulsed laser rangefinders, where high-precision time delay measurement between transmitted and received pulses is required. Proposed FPGA-based hardware implementation structure for pulsed laser rangefinder allows increase rangefinder precision. To obtain comparative performance model of computational...
The aim of this paper is to design multiplier circuits for artificial neural network applications. The efficient use of area and speed performance has become a challenging task VLSI design field. In this works, radix-4 booth multiplier and radix-2 booth multiplier algorithms are analyzed based on its area used and speed performance. The less area used means the multiplier is more efficient in usage...
The Discrete Cosine Transform (DCT) is the most widely used transform for image compression. The DCT approximation or the Binary Discrete Transform (BinDCT) [1] has shown to be a promising alternative to the DCT for its implementation simplicity, close performance and compatibility to the DCT. In this paper, we aim to present efficient VLSI architectures with a low BinDCT complexity implementation...
Reconfigurable systems based on Field-Programmable Gate Arrays (FPGAs) can offer performance and power advantages over processor-based systems as well as cost and flexibility advantages over custom integrated circuit solutions. Dynamic reconfiguration, the ability to partially modify a circuit implementation at run-time, has the potential to extend the flexibility, utilization, and resilience of FPGA-based...
This paper presents the realization of the Negative Logarithmic Function based on the FPGA chip EP2C5T144 by QuartusII software. It is designed a sequential circuit by the interpolation method and its' fast clock frequency can arrive 400MHz. It's very good that the result of the hardware test by SignalTap II.
The importance of processing of digital signals has dramatically increased due to widespread use of digital systems. A new FPGA based technique for processing of two digital signals to generate a new signal as a product of two signals is presented. The technique is based upon the use of orthogonal functions to describe digital signals.
The problems about load control system of combine and its hardware implementation are discussed. The load control system based on intelligent fuzzy control is set up. The controller is simulated on MATLAB/SIMULINK. A hardware implementation about load control system of combine based on VHDL and FPGA is proposed. According to top-down mode, the VHDL modular design of the controller is carried out,...
In conventional CORDIC algorithm, multiplier and a lookup table are needed to achieve calculation of multiple transcendental function, which will lead to hardware circuit complexity and lower operation speed. Aim at overcoming the shortcomings of traditional CORDIC algorithm, a modified CORDIC algorithm is proposed and implemented by FPGA program. The method does not need the module of correction...
In this paper, we have proposed a new architecture of RBFNN. Neural network efficiency in embedded systems offers the possibility of reconfiguration and the genericity of the solution. Indeed, the same integrated system can approximate any input-output function thanks to the parameters update on the chip. RBF neural networks constitute a subset of the neuronal networks, which has a great potential...
In this work, we investigate in a Hardware-in-the-Loop (HiL) approach to solve the problems and opportunities created by the control of large numbers (hundreds to thousands) of MEMS sensors and actuators. Using HiL simulation, one or several devices of the system are used instead of their simulated models. HiL simulation is supposed to achieve a highly realistic simulation of equipment in an operational...
Multicast switches have become indispensible for modern computer networks due to the proliferation of multicast traffic on the Internet. One important issue which greatly affects the performance of a multicast switch is how to reduce data loss caused by blocking during the process of duplication and routing of the packets. This paper proposes a multicast crossbar switch with an inner queue at each...
Communication receivers supporting multiple standards and modulation techniques are thirst of the time. Military has initiated technology like Software Defined Radio (SDR) which supports various network types and demodulation techniques. To test such devices all types of modulators which can source all possible test inputs for such receivers are needed. Instead of using off-the-shelf but costly instruments...
The hardware implementation of a high speed floating point multiplier with pipeline architecture based on FPGA is presented in the paper. In the design of the floating point multiplier, the utilization of a new radix-4 booth's encoding algorithm, the improved 4:2 compression structure and summation circuit is made to implement the compression of the partial products, and the sum and carry vectors...
The software defined radio (SDR) channel simulator is designed and implemented in the FPGA for various wireless communication systems. The dedicated short range communications (DSRC) and ultra-wideband (UWB) channels are carried out to observe the characteristics of multi-path fading channels and validate the correctness of the SDR channel simulator. The hardware reconfiguration of the fading channel...
The paper suggests the methodology for validation of designed systems and experiments through the use of the developed simulation tools and interactive models. The primary idea is prototyping on the basis of virtual visual samples imitating interacting physical objects. The desired electronic functionality is implemented in reconfigurable hardware and, therefore, can easily be changed, which significantly...
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