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Ring-shaped silicon trenches with a depth of 50 were filled with different spin-on dielectric (SOD) polymers. Ultimately, the polymer should serve as deep trench isolation layers, also called liners, for 3-D wafer-level packaging through silicon vias (TSVs). TSVs allow the vertical stacking and interconnection of multiple devices. 3-D packaging is an emerging technology that can be an alternative...
In this paper, the state-of-the-art results of research and development in wafer-level packaging (WLP) is reviewed. The paper starts from the introduction of several fan-in wafer-level packaging technologies. The focus is given on the fan-in WLP reliability performance as related to the structural differences. New failure mechanisms that appear in build-up stack layers are discussed. Next, emerging...
Wafer Level Packaging (WLP) has the highest potential for future single chip packages because the WLP is intrinsically a chip size package. The package is completed directly on the wafer then singulated by dicing for the assembly. All packaging and testing operations of the dice are replaced by whole wafer fabrication and wafer level testing. Therefore, it becomes more cost-effective with decreasing...
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