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Excellent scalability of a novel CuxSiyO emRRAM down to 22 nm node is demonstrated based on statistical data of 1 Mb test chip for the first time. The integration utilizes the standard logic process and the RRAM size is shrunk by spacer pattern technology. The reset current decreases by 5X from 130nm to 22nm node with maintaining robust data retention (10yrs. @150°C), good resistance distribution...
A novel solid-electrolyte based electrochemical induced conductive bridge (CB) resistive memory (ReRAM) is fabricated and characterized. The new device consists of a Cu-doped GeSbTe ion source, a SiO2 memory layer, and a TiTe ion buffer layer. The ion-buffer layer separates the Cu conducting path from the Cu-ion supply layer thus greatly increases the stability. This tri-layer device greatly improves...
The effects of cap layer and grain structure on electromigration (EM) reliability of Cu/low-k interconnects were investigated for the 45 nm technology node. Compared to the SiCN cap only, the CoWP capped samples showed a 40× lifetime improvement with a small lifetime variation (σ = 0.34) at the M1 level. By tuning the process parameter, Cu lines of two different grain sizes were fabricated at the...
A feasibility study of 70 nm pitch 2-level dual damascene interconnects featuring EUV lithography is presented. Using Ru barrier metal and scalable porous silica (Po-SiO, k=2.1), a low resistivity below 4.5 ????cm and a 13% reduction in wiring capacitance compared with porous SiOC (k=2.65) was obtained. The predicted circuit-performance using Po-SiO was 10% higher than that with porous SiOC. The electromigration...
A comprehensive study of low-k/Cu integration featuring short TAT (turnaround time) silylated scalable porous silica (Po-SiO, k=2.1) with high porosity (50%) is presented. The TAT for silylation is about 25% reduced by adding a promoter, causing reinforcement of the film. Applying this improved Po-SiO, 140 nm pitch dual damascene structure is successfully achieved. The wiring capacitance showed 10%...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
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