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Short-distance parallel optical links are poised to replace copper interconnects in high throughput links between computing nodes. In the receiver front-end of such systems, one- and two-dimensional monolithically integrated arrays of power- and area-efficient TIAs are required. Differential signaling is preferred for superior supply rejection while power consumption per amplifier unit should be minimized...
This paper describes the design of an optical receiver analog front end for a low power, high speed, chip-to-chip or board-to-board communication system. The circuit has been designed in 80 nm CMOS and consumes 2 mW with a 1-V supply. Using active inductors, a transimpedance gain of 62.5 dB-Omega, limiting amplifier gain of 15 dB, and overall bandwidth of 9 GHz was achieved. This work presents the...
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