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In this paper, we implemented a new algorithm in spatial domain with shell based pixel selection for watermark embedding and extraction. Here, the watermark is first converted into binary image by local thresholding and then converted into a logical matrix. Before embedding, each value of logical matrix is XOR-ed using a random 8-bit key to generate modified logical matrix. Next, the pixel of host...
In this paper, using semi-tensor product and the vector form of Boolean logical variables, the asynchronous Boolean networks under different update schemes are converted into probabilistic discrete time dynamic systems, and the structure matrix of discrete time dynamic systems is a probabilistic transaction. It provides a new way to study the properties of random Boolean networks. Under this framework,...
This contribution presents different type of serial-parallel hybrid mechanisms by group theory and logical matrix. A novel representation and logical operation of spatial mechanisms are developed. The hybrid mechanisms can be categorized into two types, closed-type and opened-type hybrid mechanisms. According to the group theory and mobility criterion, the closed-type hybrid mechanisms can be determined...
As a high level application module of SIS system, the on-line monitor and analysis system for energy-saving is widely applied to power plants. But the corresponding guide system which applied effectual guidance to realize optimal operation is still lack of sufficient research. The main purpose of the guide system is to confirm the certain reason which leads to energy loss among various reasons. Then...
As a high level application module of SIS system, the on-line monitor and analysis system for energy-saving is widely applied to power plants. But the corresponding guide system which applied effectual guidance to realize optimal operation is still lack of sufficient research. The main purpose of the guide system is to confirm the certain reason which leads to energy loss among various reasons. Then...
In the paper, we present a design of FPGA SAR processor with four 1D FFT processing elements, double internal RAM buffers and double external SDRAM modules. Without traditional corner turn phase, we propose a data layout scheme mapping one row of logical matrix into a rectangular window in physical banks of SDRAM in order to increase the practical I/O throughout between SDRAM modules and SAR processing...
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