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The authors focus on the fault modelling of external shorts in H-, C- and BiC-MOS digital circuits. In the context of functional testing, it is demonstrated that eight different electrical configurations may appear depending on the topological and technological parameters of the fault. Therefore, eight new logical models are defined showing that the wired-OR and wired-AND models, classically used...
A test set and a testable design for MOS PLAs are proposed. The new design, which modifies a PLA by adding one extra line in the AND plane and one extra line in the OR plane, can detect bridging faults. Furthermore, the design modification requires very low area overhead and is independent of the personality of the PLA under test.<<ETX>>
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