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The paper addresses here the fault model of particular type of manufacturing defects in the metal layers of deep sub-micron (DSM) chips, e.g. conductive particle contamination, bad handling or under-etching defects in the pair of parallel interconnects which lead to both severe non-zero resistive bridging fault and increased crosstalk coupling fault between the on-chip aggressor-victim interconnects...
When functional tests are used for manufacturing testing, their quality for detecting manufacturing defects needs to be evaluated. Evaluating functional tests using a traditional gate-level fault simulation environment has several disadvantages. To alleviate them, we describe a functional level coverage metric for estimating gate-level fault coverage that has a high degree of correlation to gate-level...
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