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A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
This paper studies the analog implementation of timing synchronization in impulse radio UWB systems. An insight into various UWB modulation schemes is provided, and an overview of the state-of-the art synchronization techniques is discussed. A novel method is presented for high-speed timing synchronization of UWB receivers in analog domain. The required timing resolution is determined and system-level...
The imaging laser radar is fine measure equipment for TAN with the ability to get the high precision 3D terrain. A 3D terrain matching processor was needed to be designed for the specifical application. In this paper, base on the specialty of the imaging laser radar, the3D terrain matching processor was designed, with scheme of DSP+FPGA calculating engine, multi-level memory system, flexible parallel...
In this paper, we propose a robust STBC transmission scheme to combat the timing synchronization errors over frequency-selective multiple-access channels. First, the equivalent channel model in the presence of timing synchronization errors is derived and we find that the synchronization errors result in an equivalent channel model with larger number of correlated channel taps. Based on this correlated...
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