The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The current design drivers for multi-cores, namely performance per watt, scalability and flexibility, make the Networks-on-Chip (NoCs) the de-facto on-chip interconnect. State of the art NoCs can exploit heterogeneous solutions and complex DVFS techniques to fulfill also the variability of the application requirements. Relevant showstoppers to the design of a truly flexible NoC fitting all the possible...
With the trend of growing number of integrated processing cores on Chip Multiprocessors (CMPs), researchers are working hard to increase the available parallelism of software programs so as to efficiently harness the growing computing power. One noticeable direction among these efforts is Speculative Multi-threading (SpMT), a.k.a Thread Level Speculation (TLS), which aims to extract Thread Level Parallelism...
Speculative Multi-threading (SpMT), a.k.a Thread Level Speculation (TLS), is a most noticeable research direction of automatic extraction of thread level parallelism (TLP), which is growing appealing in the multi-core and many-core era. The SpMT threads are extracted from a single thread, and are tightly coupled with data dependences. Traditional private L1 caches with coherence mechanism will not...
In this paper we introduce ICCI, a new cache organization that leverages shared cache resources and flat coherence protocols to provide inexpensive hardware cache coherence for large core counts (e.g., 512), achieving execution times close to a non-scalable sparse directory while noticeably reducing the energy consumption of the memory system. Very simple changes in the system with respect to traditional...
The snoopy protocol is a widely used scheme to maintain cache coherence. However, the protocol requires a broadcast scheme and forces substantial unnecessary data searches at the local cache. This paper proposes a novel Double Layer Counting Bloom Filter (DLCBF) to significantly reduce the redundant data searches and transmission. The DLCBF implements an extra layer of hash function and the counting...
On chip many-core systems, evolving from prior multi-pro cessor systems, are considered as a promising solution to the performance scalability and power consumption problems. The long communication distance between the traditional multi-processors makes directory-based cache coherence protocols better solutions compared to bus-based snooping protocols even with the overheads from indirections. However,...
Cache coherence protocols are major factors in achieving high performance through thread-level parallelism on multi-core systems. Among them, the token coherence protocol is the most efficient cache coherence protocol in maintaining the memory consistency. We used linear workloads such as parallel matrix multiplication to evaluate the token coherence protocol against the directory coherence protocol...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.