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This paper presents a new transceiver for impulse radio ultra-wideband (IR-UWB) systems. This work is related to CHIST-ERA SMARTER project (Smart Multifunctional Architecture and Technology for Energy aware wireless sensoRs) which address autonomous wireless sensors nodes. The ultra low-power transceiver consists of an on-off keying (OOK) modulator/demodulator and a pulse generator. To reduce power...
Now-a-days, energy considerations are major concern of every circuit design, every designer tries to minimize the energy utilization by using different techniques. In this research we have considered number of smart wireless sensor nodes and varied the supply voltage and observed the change in power dissipation due to clock frequency and total power dissipation at different frequency ranges of wireless...
Achieving low power consumption, size reduction, and space optimization are all challenges in resource-constrained wireless devices such as Wireless Sensor Network (WSN) nodes. For instance, WSN nodes use duty cycle to improve their power efficiency, and wake-up radio (WUR) is used as a control channel to wake the nodes up. With its highly flexible features, a field-programmable gate array (FPGA)...
Dynamic and Partial Reconfiguration (DPR) allows a system to be able to modify certain parts of itself during run-time. This feature gives rise to the capability of evolution: changing parts of the configuration according to the online evaluation of performance or other parameters. The evolution is achieved through a bio-inspired model in which the features of the system are identified as genes. The...
Wireless Sensor Networks (WSNs) are relatively new and challenging research area for embedded design automation. Engineering a WSN node hardware is a difficult job as the design must satisfy several constraints. Among these constraints, overall energy consumption and node size, are the two most significant constraints. WSN node platforms have until recently been designed using off-the-shelf low-power...
Traditional wireless sensor nodes are designed with low-power modules that offer limited computational performance and communication bandwidth and therefore, are generally applicable to low-sample rate intermittent monitoring applications. Nevertheless, high-sample rate monitoring applications can be realized by designing sensor nodes that can perform high-throughput in-sensor processing, while maintaining...
Achieving low power consumption, size reduction, increased efficiency, and space optimization are all challenges in Wireless Sensor Networks (WSNs). WSNs use duty cycle to improve its power efficiency, and wake-up radio (WUR) is used as a control channel to wake up WSN nodes. With its highly flexible features, a field-programmable gate array (FPGA) is one of the attractive candidates for implementing...
Wireless sensor networks (WSNs) are networks of battery-powered sensing devices connected with wireless interfaces. Energy consumption and processing efficiency are relevant characteristics for these systems, thus energy-efficient architectures are required. Recent works show that FPGAs are suitable candidates for efficient data signal processing in WSNs. In this work, we evaluate Flash-based FPGA...
Energy consumption and real-time performance are two important metrics for wireless sensor networks (WSNs). To estimate these metrics, a number of simulation environments have been developed. However, these environments were made specifically for sensor nodes with fixed architectures. The recent generation of sensor nodes often has flexible architectures through the use of programmable hardware components,...
This paper presents the architecture of a FPGA-based efficient image processing system suited to Wireless Multimedia Sensor Networks. The system consists of two major processing elements: a customized processor for the networking functions and an image processing block. The latter enables the system to detect and extract any updated objects in captured images in real-time. The proposed architecture...
A System-on-Chip (SoC) offers an optimal implementation of electronics for portable medical systems and in particular for Body Area Network (BAN) applications. It integrates as much functionality as possible into a single chip thereby allowing miniaturization of the system, while optimizing performance and power consumption. Using today's mature and cost effective semiconductor process CMOS technology...
In this paper, we present the design of a baseband System-On-Chip for tracking applications in the medical environment based on the IEEE 802.15.4 standard which can be used to track patient location in hospitals. It utilizes an ARM Cortex-M1 soft-core, 16 kb of SRAM and a bus architecture based on the AHB-Lite specification. The IEEE 802.15.4 MAC primitives are implemented in a Flash-ROM of 32 kb...
The power and reliability of communication are important factors in the design of wireless sensor networks. This paper examines the use of a shortened Reed-Solomon code for power reduction in patient-monitoring application Wireless Body Area Network. The implementations of the scheme on an 8-bit micro-controller and on an FPGA are presented. The paper compares the energy consumption of the designs...
In this paper, we provide a low cost AES core for ZigBee devices which accelerates the computation of AES algorithms. Also, by embedding the AES core, we present an efficient architecture of security accelerator satisfying the IEEE 802.15.4 specifications. In our experiments, we observed that the AES core and the security accelerator use fewer logic gates and consume lower power than other architectures...
Battery-powered sensor nodes call for low power consumption. As a crucial component, a power-efficient sensor network processor greatly reduce the overall power consumption of a node. In the paper, we propose a low-power asynchronous event-driven sensor network processor mapped onto an off-the-shelf clocked FPGA. Since the processor employs a bundled-data asynchronous encoding scheme, we define a...
Wireless sensor networks (WSNs) are typically composed of very small, battery-operated devices (sensor nodes) containing simple microprocessors with few computational resources. However, the rapidly increasing popularity of WSNs has placed increased computational demands upon these systems, due to increasingly complex operating environments and enhanced data-sensing technology. Whereas introducing...
Networks consisting of many autonomous sensors are gaining importance. Most wireless sensors have small batteries and must therefore be designed to consume very little power. In this paper, an approach for whole-system simulation for ultra-low power wireless sensor networks is proposed. To be able to estimate the power consumption of the whole network, the simulation framework must not only simulate...
We propose the use of a reconfigurable hardware architecture to reduce the power consumption of small sensor node that has various sensors and wireless communication facilities, that were the result of an adaptive function specialization mechanism. Traditional sensor nodes must have had a powerful and multi functional Micro-Controller Unit (MCU) to satisfy the requirements for processing any kinds...
In this paper we present preliminary results regarding data processing approach to energy efficiency of wireless and untethered field programmable gate array (FPGA)-based embedded systems. Re-configurability of FPGA allows for significant flexibility in its applications to embedded systems. However, high power consumption (caused by such flexibility) influences the designing process significantly...
Reconfigurable HW, like FPGAs, can improve the processing systems performance as it has been demonstrated by several research groups. Usually, the inclusion of such elements in HW platforms for Wireless Sensor Networks (WSNs) has been rejected by designers, mainly due to the power consumption penalization. A reconfigurable device allows not only performance improvement but also remote HW reconfiguration...
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