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A novel characterization setup for integrated capacitor array mismatch determination is presented. The biasing of twenty capacitor units and the selection of a specific array are controlled by externally generated digital signals. Information about the spatial matching behavior is provided for an entire MIM capacitor array, where the relevant parameters are the standard deviations ??(??Ci / C) and...
An ultra-low-power VCO based on the complementary cross-coupled structure with the three-coil transformer feedback is proposed and realized in 0.18 mum CMOS. This VCO has a 1 MHz offset phase noise of -118.5 dBc/Hz and consumes only 0.66 mW dc consumption. The FOM of this VCO is better than -195 dBc/Hz form 8.09 to 8.42 GHz, and the highest FOM of -198.6 dBc/Hz occurs at 8.2 GHz. The chip size is...
A sub-1V 50 mA low-dropout regulator (LDR) with an on-chip voltage reference is presented. This LDR utilizes the push-pull output stage to reduce the size of the power PMOS transistor. The proposed LDR with the on-chip voltage reference has been fabricated in 0.18 mum CMOS process, and its active area is 0.148 mm2. Experimental results demonstrate that the voltage reference and the LDR work for the...
This work presents the design and characterization of a CMOS-integrated thermal sensor that features a novel oscillator-based sensing interface to achieve a high thermoelectric sensitivity. The thirty pairs of thermocouples are made of n+/p+ polysilicon of a standard 0.18-mum CMOS to produce a large thermoelectric voltage. The produced thermoelectric voltage is used to control the bias current of...
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