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The objective of this paper is novel circuit design and simulation for Vernier Time-to-Digital Converter (VTDC), that is using two multi-path Gated Ring Oscillator (GRO). An 11bit VTDC with 4ps effective resolution was designed and developed for a high performance All Digital Frequency Synthesizer (ADFS). The VTDC architecture combines digital standard cells accurate and arbiter circuits to make the...
Digital implementation of analog functions is becoming attractive in CMOS ICs, given the low supply voltage of ultra-scaled processes. Particularly, all-digital PLLs are being considered for RF frequency synthesis. However, they suffer from intrinsic deficiencies making them inferior to traditional analog solutions. The investigation in this paper shows that in-band output spurs, the major shortcoming...
Time-to-digital converters (TDC) support the industry wide trend of replacing mixed-signal functionality by digital realizations. High-resolution TDCs become increasingly popular for time-of-flight measurements, full-speed testing, e.g., jitter measurement, clock and data recovery, measurement and instrumentation, and digital PLLs. As the speed leverage of technology scaling decreases below 100nm,...
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