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Circuits employing advanced performance and power management techniques (clock gating, half-cycle paths) are found to be much more sensitive to NBTI primarily due to differential and asymmetric aging, with a 1% transistor drift leading to as much as 3% circuit drift in some cases. For the first time, we report a monotonic reduction in variance of the log parameters (Ln(ΔF/F) and Ln(ΔID/ID)) as a function...
Power gating is an effective low-power design technique and is the most widely adopted leakage current reduction solution. In this project, we evaluate the effectiveness of power gating in 22 nm CMOS and analyze the impacts of the Positive/Negative Bias Temperature Instability (PBTI/NBTI) phenomenon on the power gating technique. We also estimate the actual temperatures of power gated circuits and...
The threshold voltage (VT) drift induced by negative bias temperature instability (NBTI) weakens PFETs, while positive bias temperature instability (PBTI) weakens NFETs fabricated with high-k metal-gate, respectively. These long-term VT drifts degrade SRAM cell stability, margin and performance, and may lead to functional failure over the life of usage. Additionally, most state-of-the-art SRAMs are...
Negative Bias Temperature Instability (NBTI) is a significant reliability concern for nanoscale CMOS circuits. Its effects on circuit timing can be especially pronounced for circuits with standby-mode equipped functional units because these units can be subjected to static NBTI stress for extended periods of time. This paper proposes internal node control, in which the inputs to individual gates are...
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