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The reliability of advanced embedded non-volatile memories has been discussed using the 2T-FNFN devices example. The write/erase endurance and the data retention are the most important reliability parameters. The intrinsic reliability mechanisms can be addressed through single cell evaluation, while the cell-to-cell variation determines the product level reliability. The cell-to-cell variation can...
Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
Controlled sub-nm oxide growth on (100) silicon wafers in a controlled, O2 containing ambient of a LPCVD-polysilicon deposition clustertool is demonstrated. As a comparison, a conventional LPCVD-polysilicon deposition furnace is used which generates a sub-nm oxide during loading the wafers into the heated furnace. For the first time results for different substrate doping levels are presented. Applications...
Boron segregation effects in the p-well during field oxidation can be compensated by splitting the well drive-in into two parts before and after field oxidation. In consequence sufficient field isolation can be achieved without channel stop implants even for moderate well implantation doses, keeping parasitic junction capacitances and body factors low. The smaller doping gradient between field and...
A process to form large defect-free silicon-on-insulator structures on 4-in wafers, without warpage, using a layer of oxidized porous silicon in an n/n+/n structure is presented. CMOS devices have been fabricated in insulated single-crystal silicon islands. Mobilities comparable to bulk silicon have been measured and low-leakage junctions were realized. The advantages and limitations of the process...
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