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Recently, mobile devices such as smartphones and tablets have become the most important medium for delivering internet traffic, especially multimedia content, to end users. However, mobile embedded memory incurs large power consumption owing to the highly frequent access and extensive computation. This paper presents an sizing-priority-based application-driven memory (SPIDER) design methodology for...
Flash converters have high speed conversion rate compared to other types of Analog to digital converter (ADC). As precision increases, Flash ADC requires large number of comparators compared to other ADCs. Hence, the increase in chip area, power consumption and cost of Flash converters makes trade off for many applications. So, the low power Flash ADC is aimed to be designed with less number of low...
There is no doubt that the CMOS technology scaling affects significantly the performance of the one-transistor one capacitor dynamic-random access memories (1T-1C DRAMs). In this paper, the effect of CMOS technology scaling and the change of the fabrication techniques of the access transistor and the cell-storage capacitor on the performance of DRAMs are investigated and discussed qualitatively. The...
In this paper, a new type of a 90nm CMOS LDO regulator with high load regulation using a gain goost-up technique. The development of low drop-out (LDO) regulator architectures in the power management family is necessary to reduce the standby power of portable applications such as cellular phones and PDAs. In essence, this LDO regulator suffers from an inherent load regulation which impedes to work...
In this paper, a novel readout scheme for the one-transistor one capacitor (1T-1C) DRAM will be introduced. The scheme depends on charging the bitline as well as the cell-storage capacitance to a certain level and comparing the charging current with a reference current to disclose the stored data. The factors affecting the sense margin will be discussed. The proposed readout scheme will be verified...
The Adder is the important part in any processor/controller design. Till date there are a plenty of 1-bit full-adder circuits which have been proposed and designed. In this paper we have a analytic and comparative description of various full adder circuits, considering various constraints like power consumption, speed of operation and area. The circuits are designed in the virtuoso platform, using...
As compared to static logic, domino logic circuits are always preferable for high performance circuit designs because of their less number of transistor requirement and high operational speed. Due to the presence of charge sharing problem and less noise tolerance this logic is not broadly accepted for all logic designs. The desired output of the circuit can change with a little noise pulse in the...
Cache memory plays an important role in high speed electronic devices. SRAM is the key element of cache memory. Cache memory is used for their high speed and SRAM is the element which provides speed to the cache. So this work is mainly concentrated on the simulation and analysis of 8T SRAM cells and their comparative analysis of different parameters such as width to length ratio, capacitance and power...
Domino logic circuits are most often used in high performance designs such as microprocessors because of high speed and less area over the static logic. But these domino logics suffer from high power dissipation and low noise tolerance. In this paper the earlier proposed techniques to reduce power consumption of Domino logic such as Dual Threshold Voltage (DTV), Dual Threshold Voltage-Voltage Scaling...
Leakage currents are one of the major design concerns in Deep sub-micron (DSM) technology due to rapid integration of semiconductor industries by reducing the transistor size. Many parameter has been reduces with technology scaling such as Threshold voltage, oxide thickness, channel length and supply voltage (Vdd) has been reduced to keep power consumption under control. As a consequence, the transistor...
Power consumption is becoming an increasingly important component of processor design. As technology node shrinks both static and dynamic power become more relevant. This is particularly critical for the cache hierarchy. Previous implementations mainly focus on reducing only one kind of power in the cache, either static or dynamic. However, for a more robust approach that will remain relevant as technology...
Dynamic domino logic circuits are used for high system performance. The dynamic circuits offer superior speed and power dissipation over static CMOS circuits. But these circuits suffer from limitations such as charge leakage, noise and charge sharing. This article provides analysis of the different keeper topologies on pseudo domino logic circuits with reference to power dissipation. The circuit simulations...
Dynamic logic style is mainly used for high fan in and high performance circuits because of its smaller area and fast superior speed. This style comes with a problem of low noise margin which makes it more susceptible to noise than static CMOS circuits. It also faces some charge sharing and leakage problems. A small amount of noise at the input can cause an undesirable change at the output. Domino...
The rapid growth in CMOS technology with the shrinking device size towards 22 nm has allowed for placement of billions of transistors on a single microprocessor chip. To achieve very high system performance, domino logic styles are widely employed in high performance VLSI chips together with aggressive technology scaling. Comparators are widely used in central processing units (CPUs) and microcontrollers...
CMOS logic is extensively used in VLSI circuits but due to scaling of technology, the threshold voltage of the transistors used in CMOS circuits decrease which cause an increase in leakage power. Dynamic power consumption, which is proportional to square of supply voltage VDD further adds to the overall power dissipation. This results in low battery life of mobile devices. In this brief, a novel method...
Multiple Dynamic Supply Voltage (MDSV) is a technique that focuses on reducing the dynamic power. This technique is an evolution of the Multiple Supply Voltage (MSV). MSV and MDSV introduce some difference on traditional physical synthesis due to the different voltage operations of each region in the design. To convert the voltage among regions supplied by different voltages, these techniques insert...
A new low power dynamic CMOS one bit full adder cell is presented. In this design technique is based on semi-domino logic. This new cell is compared with some previous proposed widely used dynamic adders as well as other conventional architectures. Objective of this work is to inspect the power, delay, power-delay-product and leakage performance of low voltage full adder cells in different CMOS logic...
This paper presents some proposed and new techniques in comparison to a traditional one for register-transfer level (RTL) circuits. The traditional technique focuses on killing glitches in both the control and data path parts of the circuit to reduce power consumption. By analyzing and simulating the generation and propagation of glitches in some benchmark circuits, we found out some issues when killing...
This paper presents results of analyses of full adders structures to build of low-power adders for specific data. At first four 1-bit full adder cells were selected from literature, designed in UMC 180nm technology and simulated for assessment of theirs energetic and time parameters. Extended power consumption model, taking into consideration input vector changes, was used, giving more accurate values...
Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS...
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