The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Power on chip is highly temperature dependent in deep sub-micron VLSI. With increasing power density in modern 3D-IC and SiP, thermal induced reliability and performance issues such as leakage power and electromigration must be taken into consideration in the system level design. This paper presents a new methodology to accurately and efficiently predict power and temperature distribution for 3D ICs.
A reliable and accurate analytical model is desired for the printed circuit board (PCB) with IC package to predict the system response due to loadings such as shock and vibration simulation or even with thermal effect. This work addresses the procedure of model verification by the adoption of experimental modal analysis (EMA) to validate the finite element (FE) model constructed by FE commercial software...
Thermal analysis has long been essential for designing reliable, high-performance, cost-effective integrated circuits (ICs). Increasing power densities are making this problem more important. Characterizing the thermal profile of an IC quickly enough to allow feedback on the thermal effects of tentative design changes is a daunting problem, and its complexity is increasing. The move to nanoscale fabrication...
In this paper, we examine the thermal issues in 3-D ICs by system-level modeling of power dissipation and analytical and numerical modeling of deviceand package-level heat removal. We find that for comparable system performance in 2-D and 3-D ICs, 20%-25% reduction in power dissipation can be achieved by 3-D integration due to lower capacitance associated with interconnects and clock networks. If...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.