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Clock skew scheduling is an effective technique in performance optimization of sequential circuits. However, with process variations, it becomes more difficult to reliably implement a wide spectrum of clock delays at the registers. Multidomain clock skew scheduling is a good option to overcome this limitation. In this paper, we propose a practical method to efficiently and optimally solve this problem...
It is well known that the combination of clock skew scheduling and delay insertion can achieve the lower bound of sequential timing optimization. Previous approaches focus on the minimization of required inserted delay. However, from the viewpoint of design closure, minimizing the number of inserted buffers is also very important. In this paper, we propose a linear program to minimize the number of...
An inherent performance gap between custom designs and ASICs is one of the reasons why many designers still start their designs from register transfer level (RTL) description rather than from behavioral description, which can be synthesized to RTL via high-level synthesis (HLS). Sequencing overhead is one of the factors for this performance gap; the choice between latch and flip-flop is not typically...
In deep submicron technology, wire delay is no longer negligible and is gradually becoming a dominant factor of system performance. Several state-of-the-art architectural synthesis flows have already adopted the distributed register architecture to cope with the increasing wire delay by allowing multicycle communication. In this paper, we formulate channel and register allocation within a refined...
One solution to the timing closure problem is to perform infrequent operations in more than one cycle. Despite simplicity of the solution statement, it is not easily considered because it requires changes in RTL, which, in turn, exacerbates the verification problem. We offer a timing closure solution guaranteed to preserve functional correctness of designs expressed using atomic actions or rules....
Inter team communication within a software project team is currently cumbersome considering the globally distributed development nature of software projects. We have designed a novel approach based on mobile multi-agent technology that would assist the members of a project teams in effectively communicating within themselves in scheduling meetings and relay of other information among globally distributed...
A complete power-aware high-level synthesis algorithm is presented. It performs the schedule, resource allocation and binding of behavioral specifications. It overcomes the limitations of low-power algorithms and based on a bit-level timing model and a study of the target technology, tries to chain in the same cycle as many operations as possible. It also fragments the functional units, not the operations,...
Statistical static timing analysis (SSTA) methods, which model process variations statistically as probability distribution functions (PDFs) rather than deterministically, have emerged to more accurately portray integrated circuit performance. This analysis has been thoroughly performed on traditional zero clock skew circuits where the synchronizing clock signal is assumed to arrive in phase with...
It has been shown that several process parameters encounter variation in the DSM era. Consequently, several techniques, such as statistical gate sizing and clock skew scheduling, have been proposed to enhance yield loss. In this work, we propose an integrated statistical framework for gate sizing and skew scheduling in order to minimize yield loss and area cost. While traditional separate methods...
The scheduling of timed tasks is generally based, at the hardware level, upon the use of time intervals. For example, most microprocessor families provide their only hardware support for timing control in the form of a programmable interval timer chip accessible as an I/O device over the system bus. In this paper we will argue that a more natural and elegant solution bases timing on a local (to a...
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