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In this paper a BISR architecture for embedded memories is presented. The proposed scheme utilises a multiple bank cache-like memory for repairs. Statistical analysis is used for minimisation of the total resources required to achieve a very high fault coverage. Simulation results show that the proposed BISR scheme is characterised by high efficiency and low area overhead, even for high defect densities...
Three dimensional memory systems has been argued as a potential pathway in solving the ever growing difference between comparative speeds of CPU and memory systems. In this paper, we describe a three-tier, three-dimensional SRAM macro that has been designed and fabricated in a 0.18 um FD-SOI CMOS technology. 3D stacking is found to improve wire latency as compared to planar memory structure although...
In the imaging algorithms of Inverse Synthetic Aperture Sonar (ISAS), Range-Doppler Algorithm (RDA) and Polar Formation Algorithm (PFA) can be only suitable for far-field imaging. For obtaining near-field imaging, Computed Tomography Algorithm (CTA) is introduced. Five point-targets in near-field at different locations are imaged with RDA, PFA and CTA, respectively. Imaging results show that five...
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