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The bottom-up self-assembly fabrication process of nanoelectronic results in higher defect density. Furthermore, transient and permanent faults could also occur during operation due to the sensitivity. Thus, defect and fault tolerance techniques are urgently needed. In this paper, we propose a concept of diversity mapping and three corresponding algorithms for defect-tolerance logic mapping in nanoelectronic...
In addition to high defect density, serious variations exist in self-assembled nanoelectronic crossbar architectures compared to the conventional lithography-based CMOS integrated circuits. Therefore, it is one of the emerging challenges to tolerate variations apart from tolerating defects. In addition, considering many-sided factors simultaneously in variation tolerance is necessary. In this paper,...
In hybrid nano-architectures, self-assembled nanoscale crossbars are fabricated on top of a reliable CMOS subsystem. Bottom-up self-assembly nanofabrication process, used in nano-architectures, yields nanodevices with significantly more variations compared to the conventional top-down lithography used in CMOS fabrication. This is in addition to an increased defect density expected for self-assembled...
Programmable logic arrays (PLAs) using self-assembly nanowire crossbars have shown promising potential for future nano-scale circuit design. However, due to the density and size factors of nanowires and molecular switches, the fabrication fault densities are much higher than those of the conventional silicon technology, and hence pose greater design challenges. In this paper, we propose a novel defect-aware...
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