The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
In this work, crossbars with memristors down to 40x40 nm2 in size were fabricated by hybrid process combining optical and e-beam lithography. The developed process provides ~90% <<yield of forming-free>> nanodevices exhibiting memristive properties with endurance up to 105 cycles, making this approach suitable for neuromorphic applications.
A novel CMOS compatible photo oxidation (PO) technology is proposed in this paper which, by only using standard DUV photo lithography process, demonstrates a strong oxidation capability to form CMOS compatible WOx. The oxidation occurs through catalytic chemical reaction during the post exposure baking (PEB) process. Based on this unique PO process, a high performance forming free 1T-1R WOx ReRAM...
Three metal level 56nm-pitch Cu dual damascene interconnects in k2.7 low-k ILD have been demonstrated by using sidewall-image-transfer (SIT) patterning scheme to investigate the feasibility of the SIT process for sub 50nm-pitch technology node. 45nm-pitch line resistance (R) and capacitance (C) simulation are performed to estimate the R-C variation for double patterning schemes. The photoresist mandrel...
Tungsten-based full metal gate (FMG) stacks that are equivalent to or better than metal-inserted poly-Si (MIPS) stack have been developed. These fully encapsulated FMG stacks enable borderless source/drain contacts needed for the 14 nm technology node and beyond, where the contacted gate pitch is expected to be less than 80 nm. Tungsten replaces gate salicidation with the sheet resistance ≤ 14 Ω/□...
Dual damascene integration was applied to High Density Through Silicon Vias in order to provide a low-cost TSV process. The architecture was developed for 3 μm-width and 20 μm-height vias to fit electrical and morphological requirements. Electrical results show the manufacturability of the process (>;95% yield). Using LETI internal cost model, we estimate a cost reduction of 23% compared to single...
To increase memory bandwidth with minimum area overhead, the new concept of 3D-stacked memory structure consisting of a small sense amplifier shared with a few 3D memory cells has been presented. The 16 bit 3D-stacked TiO2 memory chip was fabricated and demonstrated. The estimated bandwidth per unit area of 3D-stacked memory in sub-65 nm CMOS technology indicates that the 3D-stacked memory has potential...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.