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This paper describes a real-time implementation of timestamp-free network synchronization using RF signaling between a master and slave node. Rather than conventional approaches of exchanging digital timestamps through a dedicated synchronization protocol, timestamp-free synchronization is performed implicitly at the physical layer through timing of a master node's responses to a slave node. This...
Underwater wireless communication is greatly attractive to explore and develop because there is a vast unexploited area under the sea. Therefore, the effect of skew is not negligible when we use sound waves in water for wireless communication. For underwater sensor or cellular networks, some time synchronization protocols which consider the skew such as Time Synchronization for High Latency (TSHL)...
The latest IEEE WLAN 802.11ad standard guarantees the multi giga bit throughput which is highest in the Wireless LAN (WLAN) technology. The system designed for such high performance will pose enough design challenges to make them consume low power. This can however be achieved by adopting low power management and control block in the digital part of the System on Chip (SoC) like Medium Access Control...
The link between the processor and memory is one of the last remaining parallel buses and a major performance bottleneck in computer systems. The Hybrid Memory Cube (HMC) was developed with the goal of helping overcome this ’memory wall’. In contrast to DDRx memory interfaces, the HMC host interface is serial and packetized. This paper presents a vendor-agnostic, open-source implementation of an HMC...
Recent statistics show an increase in environmental disasters, a fact which is also perceivable to the public as reports of avalanches, earthquakes and landslides mount in media coverage. Search and Rescue with modern localization techniques consequently attracts attention from scientific and industrial sides. This paper introduces one part of the I-LOV project, endorsed by the Federal Ministry of...
A tag simulator is a device that can exchange data with an RFID reader in the same way as a real transponder. It may be of help for reader developers in the process of testing the device response and adjusting the communication algorithms. It may equally help system integrators in testing and tuning the performance of the complete RFID system that comprises the readers, the network to which they are...
This paper proposes a synch-free RF Time-of-Flight (ToF) measurement system as an epoch-making protocol of RF ToF ranging for wireless sensor networks (WSNs). This system is based on vernier effect due to two heterogeneous clocks, which are basically adopted in order to generate new virtual time resolution much smaller than the intrinsic time resolution of two clocks of which the ratio is n:(n-1)...
In this paper, an ultra-low-power baseband processor for a UHF Passive RFID Tag is presented. It proposes a prominent RFID tag baseband architecture which is compliant with the ISO18000-6B UHF RFID protocol. Several low-power design approaches are employed to reduce the power consumption, including low voltage low operation frequency approach, clock gating technique, clock strobe design, asynchronous...
Passive UHF RFID transponders (tags, in short) are mixed-signal Systems-on-Chip (SoCs) for remotely powered communications which must comply with stringent requirements on current consumption. This brief focuses on the design of a backend digital processor for UHF RFID tags targeting the Class-1 Generation- 2 EPC Protocol, and proposes different techniques for reducing its power consumption. After...
In recent years, radio frequency identification (RFID) UHF technology receives great attention because of its wide use in many fields. UHF RFID enables identification from a long distance unlike earlier bar-code technology. RFID tag plays one of the most important roles in logistics and passive RFID tag is the most valuable applications due to its low cost and long recognition distance. Therefore...
This paper introduces a verification development platform for RFID reader. The RFID reader is compatible with EPC Class-1, Generation-2 Standard, operating at the 915 MHz band. The UHF RFID reader includes RF analog front end (AFE), the base band and clock. The RFID RF AFE contains transmitting circuit, receiving circuit, frequency synthesize, circulator, etc. The base band contains the FPGA chip,...
This paper introduces a system design for RFID reader. The RFID reader is compatible with EPC Class-1, Generation-2 Standard, operating at the 915 MHz band. The UHF RFID reader includes RF analog front end (AFE), the base band design and clock control. The RFID RF AFE contains transmitting circuit, receiving circuit, frequency synthesize, circulator, etc. The base band contains the FPGA chip, 100...
Multiprocessor deterministic replay has many potential uses in the era of multicore computing, including enhanced debugging, fault tolerance, and intrusion detection. While sources of nondeterminism in a uniprocessor can be recorded efficiently in software, it seems likely that hardware support will be needed in a multiprocessor environment where the outcome of memory races must also be recorded....
Bluetooth communication is based on frequency hopping spread-spectrum and time division duplexing. Bluetooth devices must be properly synchronized so that they can hop together; the synchronization is done by using the same channel set as well as the same hopping sequence within that channel set along with the time synchronization. Frequency hopping sequences are derived from Bluetooth device addresses...
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