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Built-in self-test (BIST) is one of the most widely used design-for-testability (DFT) techniques, particularly for embedded random access memory (RAM). To ease the test and diagnosis flow, we have previously developed a synthesis compiler, called BRAINS which stands for BIST for RAM in Seconds. It possesses many nice features, such as accessibility, scalability, programmability, and flexibility, thereby...
Built-in-self-repair is an enabling approach for improving memory yield in system-on-chip designs. Reducing the overhead of repair circuits while minimizing the test and repair time is of prime importance. This article presents a fast parallel repair methodology for SoC memory cores and an associated automation framework.
Built-in self-repair (BISR) is one promising approach for improving the yield of memory cores in an system-on-chip (SOC). This paper presents a test scheduling approach for BISR memory cores under the constraint of maximum power consumption. An efficient test scheduling algorithm based on the early-abort probability is proposed. Experimental results show that the scheduled results of the proposed...
Network-on-chip is one popular interconnection infrastructure for giga-scale integrated chips. Moreover, the number of memory cores in such chips usually is very large. This paper proposes an efficient built-in self-repair (BISR) method for repairing memories in NoCs. By reusing the communication links in NoCs, the BISR scheme can repair multiple memories using one BISR circuit without incurring the...
This paper presents a built-in self-test (BIST) approach to test embedded memory blocks in configurable system-on-chips (SoCs). The idea of this paper is to develop BIST architecture and BIST configurations for testing embedded memory blocks in Xilinx Virtexl-4 series SoCs by using an embedded FPGA core. The proposed approach tests RAMs operating in all of different sizes both in single-port and dual-...
Multicore system-on-chip (SOC) design is widely used for current high-performance applications. Multicore SOCs typically include a large amount of homogeneous memory cores (i.e., memory cores have the same size and configuration). This paper proposes a pipelined built-in self-test (PBIST) scheme for homogeneous memory cores in multicore SOCs. A PBIST circuit can be shared by clustered multiple homogeneous...
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