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Static RAM with a traditional topology of DICE designed by scaling with rules less than 65-nm lost advantages in failure tolerance to single nuclear particles compared to CMOS RAM on 6-T memory cells. Transistors of the STG DICE cell have been separated onto two groups so that impact of single nuclear particles on one of the groups do not lead to an upset of the logic state of the cell, but only causes...
Multiport CMOS cell with the soft-error immunity based on DICE which is divided into two spaced groups of transistors each of them consisting of four transistors. The larger the distance between these two CMOS transistor groups, a multiport SRAM is more hardened to single event upsets. The result of a single nuclear particle strike only on the one transistor group of a DICE trigger is a single-event...
Low power design has become one of the primary focuses in digital VLSI circuits. Technology scaling demands a decrease in both supply voltage (VDD) and threshold voltage (VTH). This leads to increase in sub-threshold leakage power. In VLSI chips, the power consumption is more in Flip-Flops. So the primary objective of using sub-threshold circuits is to reduce the energy. This paper presents about...
In this paper, the authors demonstrate a standard cell-based circuit technique fully operational at supply voltages between 84 mV and 62 mV in standard 0.13 μm bulk CMOS depending on the area overhead invested. Supply voltage reduction is limited by the degradation of the on/off current-ratio of CMOS transistors with decreasing VDD, causing the leakage currents through the off transistors to be on...
The use of current to switch nanomagnets has opened up opportunities for using spin-torque-transfer (STT) based magnetic memories in embedded applications. This paper presents a design space exploration of 1T-1STT MTJ arrays for embedded applications, under variations and disturbs conditions.
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