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Built-in self-repair (BISR) techniques have been widely used to enhance the yield of embedded memories. Built-in redundancy-analysis (BIRA) module is one key component of the BISR circuit. In this paper, we present a BIRA scheme for random access memories (RAMs) with 3D redundancy to improve the yield of RAMs with cluster faults. A RAM with 3D redundancy is equipped with spare rows, spare columns,...
Reliability, availability, and maintainability (RAM) are three very important and necessary disciplines that must be applied within the system engineering process to ensure program success. The best way to generate success for a system is to overlay reliability engineering principles on the system engineering lifecycle, applying a phase-by-phase approach to drive RAM into the design. Beginning very...
Three-dimensional (3D) integration technology using through silicon via (TSV) is an emerging technology for integrated circuit designs. Random access memory (RAM) is one good candidate for using the 3D integration technology. Introducing redundancies into a large-capacity RAM in design phase is essential for yield improvement. In this paper, we present yield-enhancement techniques for 3D RAMs. In...
Built-in-self-repair is an enabling approach for improving memory yield in system-on-chip designs. Reducing the overhead of repair circuits while minimizing the test and repair time is of prime importance. This article presents a fast parallel repair methodology for SoC memory cores and an associated automation framework.
Built-in self-repair (BISR) is one promising approach for improving the yield of memory cores in an system-on-chip (SOC). This paper presents a test scheduling approach for BISR memory cores under the constraint of maximum power consumption. An efficient test scheduling algorithm based on the early-abort probability is proposed. Experimental results show that the scheduled results of the proposed...
Network-on-chip is one popular interconnection infrastructure for giga-scale integrated chips. Moreover, the number of memory cores in such chips usually is very large. This paper proposes an efficient built-in self-repair (BISR) method for repairing memories in NoCs. By reusing the communication links in NoCs, the BISR scheme can repair multiple memories using one BISR circuit without incurring the...
Life Cycle Cost (LCC) is used as a cost effective decision support for maintenance of railway track infrastructure. However, a fair degree of uncertainty associated with the estimation of LCC is due to the statistical characteristics of Reliability, Availability and Maintainability (RAM) parameters. This paper illustrates a methodology for estimation of uncertainty linked with LCC, by a combination...
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