The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
An over-2Gbps SSO analysis for a low-cost wire-bonding type BGA package with 32bit DDR interface is demonstrated. The analysis is based on the true transistor-level signal-power integrity simulation, a large-scale, full-wave, full-three dimensional BEM field solver package model and return-path decomposition method which eliminates artificial return-path discontinuities. The simulation results suggests...
This paper presents a Volterra-based method of behavioral modeling for the I/O buffers of digital ICs. While this technique brings a slight improvement in accuracy over previous ones, its main strength is a greater degree of generality. With a modeling approach less dependent on the nature of the devices and more easily extendable to include the effects of multiple inputs one may hope better meet...
A novel bandgap reference based on CMOS technology is presented in this paper. The main feature of the circuit is the wide input voltage range. It consists of two stages based on voltage-connection, for the first stage an improved structure is adopted to provide the relative high output voltage and for the second stage an amplifier is used to ensure the high accuracy. The circuit is simulated with...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
This paper addresses the generation of enhanced models of the input/output buffers of digital integrated circuits. The proposed models overcome the current limitations of the state-of-the-art models and can be obtained from device port transient responses only. They can be effectively implemented as SPICE subcircuits in any commercial tool for signal integrity or core noise simulations.
This paper describes a push-pull parametric transformer constructed using a pair of orthogonal-cores. The operating characteristics of the parametric transformer with a rectifier load were analyzed based on SPICE simulations. The analysis results show good agreement with experiment. It was found that the input surge current of the full-wave rectifier circuit with a smoothing capacitor can be compensated...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.