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This paper describes the analysis of power generating units and their implementation, these are located within the technological centre in Ostrava-Vitkovice. Further issues concerned in this paper deal with digital simulation using computer model created using the EMTP — ATP software to evaluate particular process courses that may occur on the power inverter installed in the technological centre....
This paper explores microarchitecture controlled proactive gain boosting as a means of lowering the effects of supply voltage droop in digital circuits powered by embedded, all-digital linear regulators. A behavioral power supply rejection model for all-digital linear regulator is presented. The presented regulator shows enhanced power supply rejection under increased operating frequency. Test-chip...
Today, the consumer market calls for high-performance power supply systems. Existing sources and technologies are not abreast of portable electronics trends, thus pressing both the academic and industrial research to focus on innovative technologies. Customers' requirements lead to a growing interest in longer-lasting power, fast transient response power supply systems and a minimization of system...
The purpose of TAFT fault tolerance studies conducted at CNES is to prepare the space community for the significant evolution linked to the usage of COTS components for developing spacecraft supercomputers. CNES has patented the DMT and DT2 fault-tolerant architectures with 'light' features. The development of a DMT/DT2 testbench based on a PowerPC7448 microprocessor from e2v is presented in this...
This paper describes a comparative analysis between two topologies of operational amplifiers to design a 40 MS/s 12-bit pipeline analog to digital converter (ADC). The analysis includes AC and transient simulation to select the proper topology. This ADC is implemented in a 0.35 mum AMS CMOS technology with 3.3 V single power supply. The capacitors and selected operational amplifiers were scaled for...
The design of a full integrated electronics readout for the next ILC ECAL presents many challenges. Low power dissipation is required, and it will be necessary to integrate together the very front-end stages with an analog to digital converter. We present here a 12 bit 30 MHz analog to digital converter using a pipelined architecture. It is composed by ten 1.5 bit sub-ADC with a final 2 bit flash...
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