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A regulated linear dual-tuning differential ring oscillator has been designed and fabricated in UMC 0.13 µm CMOS process for ultra wide band (UWB) applications. The integrated voltage regulator has a robust performance with high power supply rejection ratio to improve phase noise performance at the presence of power supply ripple. The proposed dual-tuning technique enables a wide tuning range covering...
Operating circuits in the subthreshold region is a simple method to lower total power consumption. The lower supply voltages decrease the electric fields present in the devices (resulting in lower charge collection), but increase the time required to remove the charge. These two competing mechanisms are characterized through two-photon absorption experiments for single-events to show that single-event...
This paper presents new theoretical results on the phase noise of a class of unsaturated ring oscillators. These new results focus on cycle-to-cycle correlation as a source of timing jitter and highlight its importance in contributing to the phase noise of these unsaturated ring oscillators. Because the outputs of saturated ring oscillators always reach the power supply, such cycle-to-cycle correlation...
Polymorphic gates can be considered as a new reconfigurable technology capable of integrating logic functions with sensing in a single compact structure. Polymorphic gates whose logic function can be controlled by the level of the power supply voltage (Vdd) represent a special class of polymorphic gates. A new polymorphic NAND/NOR gate controlled by Vdd is presented. This gate was fabricated and utilized...
Continuous scaling, necessary for enhanced performance and cost reduction, has pushed existing CMOS materials much closer to their intrinsic reliability limits, forcing reliability engineers to get a better understanding of circuit failure. This requires that designers will have to be very careful with phenomena such as high current densities or voltage overshoots. In addition to the reliability issues,...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
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