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Clock distribution networks are affected by different sources of variations. The resulting clock uncertainty significantly affects the frequency of a circuit. To support this analysis, a statistical model of skitter, which consists of clock skew and jitter, for 3-D clock trees is introduced. The effect of skitter on both the setup and hold time slacks is modeled. The variation of skitter is shown...
This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
A new series of all solid state nanosecond pulse generators for accelerator applications with amplitude from 100 kV to hundreds of volts has been developed. Pulse duration can be formed from 1 ns to several hundreds of nanoseconds, rise time is from 0,1 ns to several nanoseconds with peak power of several hundreds of megawatts. Pulse repetition rate can reach several kilohertz in continuous or burst...
This article presents the design and experimental results of a 3rd order lowpass ΣΔ modulator using a continuous-time loopfilter. The modulator was implemented in a 0.5µm 3.3 V CMOS technology with standard threshold voltages. The ΣΔ modulator feature 80dB dynamic range and a resolution of 12 bit in the bandwidth of 25kHz. The measured power consumption is only 250 µW from a single 1.5V supply.
Substrate coupling between a noise-generating digital circuit and analog PLL's realized in a standard low-resistivity substrate 0.25µm CMOS process is analyzed. It is found that the main source of jitter strongly depends on the power supply configuration of the PLL.
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