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A methodology for DC–DC conversion in three-dimensional (3-D) circuits is described in this paper. The proposed approach exploits both linear and switching buck converters with different conversion ranges, thereby increasing power efficiency. By replacing the traditional LC filter within a switching converter with a distributed filter, a significant increase in efficiency is demonstrated. Additionally,...
In this paper, a high-accuracy CMOS on-chip RC oscillator (OSC) for MCU application is presented. The oscillator can provide a 16 MHz output frequency with the total accuracy in ±1% in all process corner at 1.8 v and 55°C condition, ±2% in all process, supply voltage and temperature condition after 7bit digital trimming. This design features low sensitivity to power supply from 1.8 v to 6.0 v and...
This paper presents a power supply module (PSM) for SoCs (system on chip). This module, which is based on an improved LDO, has a wide input range and switchable power path. The proposed PSM can output a steady voltage of 6v as input voltage varies between 5.7 V-30 V, with a max error of 4.3%. It also provides a flexible power path. The SoCs will be supplied by either internal LDO or external power...
A technique for managing leakage in level shifters used in SoCs to transfer digital signals across supply domains is introduced. The technique is effective regardless of supply sequencing order or availability, and it ensures a deterministic output from all level shifters under all supply conditions.
Combining the supply ripple subtraction and high-pass filtering can improve the power supply rejection (PSR) over wideband frequency of low dropout regulator (LDO). The proposed LDO is fabricated by TSMC 0.35 ??m 2-poly 4-metal CMOS process. The simulation results at maximum load current of 100 mA, show that PSR at 10 k, 100 k and 1 M are -72 dB, -75 dB and -46 dB, respectively. Therefore, it's well...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
An on-chip buck converter with 3D chip stacking is proposed and the operation is experimentally verified. The manufactured converter achieves a maximum power efficiency of 62% for an output current of 70mA with a switching frequency of 200MHz and a 2x2mm on-chip LC output filter in 0.35mum CMOS. The use of glass epoxy interposer to increase the maximum power efficiency up to 71.3%, and the power efficiency...
In this work, the bulk-gate controlled circuit to improve the power supply ripple ratio (PSRR) of a Low Dropout Regulator (LDO) which deteriorates due to lowering power consumption is proposed. Designing with 0.25 mum CMOS process, the simulation results by HSPICE shown that the proposed circuit provides a high performance of PSRR even though 1/10 of the power consumption is reduced compare to the...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
Different types of voltage reduction circuits for application to VLSI-DRAMs have been investigated. A lumped element network description of the circuits and the distributed power supply of a 4Mbit chip has been developed to model the load characteristic of the memory in a realistic way. It is shown, that the peak currents in the active cycle can be delivered by the distributed capacities of the supply...
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