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In this paper, we will present a diagnostic test case of a hard-to-find fail condition causing an unexpected partial power on of a chip fabricated in IBM 65 nm bulk technology. In particular, we will describe the fail condition as well as the combined use of electrical testing, optical methodologies, and detailed circuit analysis that were used to reach a successful root cause identification of the...
This paper explores the concept of developing a bondpad-less fully-integrated inductive link for power/data transfer between a CMOS Integrated Circuit (IC) and a PCB. A key feature of the implemented system is that it requires no off-chip components. The proposed chip uses a standard 0.35 µm process and occupies an area of 2.5mm×2.5mm and an on-chip inductor occupies an area of 1.5mm×1.5mm. At 900MHz,...
In this paper, the modeling and analysis of power supply noise effects on analog-to-digital converter (ADC) with chip-Package-PCB hierarchical power distribution network (PDN) is proposed. Especially, this research is focused on the PDN structure, which includes power/ground Through-Silicon-Via (TSV) for the case study of various PDN structures. The analysis was progressed with a frequency range from...
In recent years, in order to handle various sources of noise (including substrate and power supply noises) and process variation in high-end mixed-signal circuit design, analog circuits are often required to be placed symmetrically to the common axis, and high noise digital circuits need to be placed far away from noise interference to the analog blocks. In this paper, we obtain the mixed-signal SoC...
3D contactless technology based on capacitive coupling represents a promising solution for high-speed and low power signaling in vertically integrated chips. AC coupled interconnects do not suffer from mechanical stress, and the parasitic load is much reduced when compared to standard DC solutions, such as wire bonding and micro bumps. Communication system based on wireless interconnection scheme...
In this paper, the effect of power supply noise imbalance on 900 MHz differential low noise amplifier (LNA) output is investigated. Chip and package (PKG) power distribution network (PDN) are modeled with lumped components to estimate the power supply noise imbalance. Also an equivalent circuit of differential LNA is modeled to estimate the noise voltage at differential LNA output and verified through...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
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