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An analog-to-digital converter (ADC) is an essential device in mixed mode systems. The performance of the ADC, however, is deteriorated by coupled power supply noises through hierarchical chip-PCB power distributed networks (PDNs). In order to design a high-performance system, modeling and analysis of power supply noise effects on the ADC are necessary, as the power supply noise is coupled to the...
A high-precision low-voltage adaptively biased (AB) low-dropout regulator (LDR) with extended loop bandwidth is proposed. The multistage output-capacitor-free LDR is stabilized by Miller compensation and Q-reduction techniques to reduce the required minimum load current. Adaptive biasing is achieved by using direct current feedback from a simple current mirror. The dynamics of both the main feedback...
A technique for managing leakage in level shifters used in SoCs to transfer digital signals across supply domains is introduced. The technique is effective regardless of supply sequencing order or availability, and it ensures a deterministic output from all level shifters under all supply conditions.
This paper deals with the design of power supply distribution network in CMOS System-on-Chips to reduce electromagnetic emissions. The main sources of both conducted and radiated emissions are pointed out and the most popular solutions for these problems are summarized. Based on that, the paper shows a new power supply network and grounding scheme that strongly mitigate the off-chip propagation of...
The implementation of complex functionality in low-power nano-CMOS technologies leads to enhance susceptibility to parametric disturbances (environmental, and operation-dependent). The purpose of this paper is to present recent improvements on a methodology to exploit power-supply voltage and temperature variations in order to produce fault-tolerant structural solutions. First, the proposed methodology...
Data retention power gating is a commonly used method for leakage reduction in deep submicron SRAM. However, application of such methods result into reduced stability of the SRAM bitcell. Moreover, reducing supply voltage and increasing process variation put a limitation on such usage in deep submicron processes. Present scheme describes a method to enhance stability while applying such data retention...
We propose a dynamic voltage boosting (DVB) method for improving performance by slightly boosting voltage within a withstand voltage. We measured an improvement of 44%voltage drop with about 10 % area overhead in a 65 nm CMOS. This DVB method combined with a series power gating can be used to achieve high performance for low-cost low-power SoCs in advanced process technology.
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