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Excessive capture power in at-speed scan testing may cause timing failures, resulting in test-induced yield loss. This has made capture-safety checking mandatory for test vectors. This paper presents a novel metric, called the TTR (Transition-Time-Relation-based) metric, which takes transition time relations into consideration in capture-safety checking. Capture-safety checking with the TTR metric...
This document presents a compilation of results from tests performed by iRoC Technologies on SER induced by alpha particles on SRAM memories for technology nodes from 180 nm to 65 nm. The aim of this study is to establish the variation of sensitivity with technology node for SEU and MCU, and to analyze the possible influence of different designs and technological parameters at a given technology node.
Transient faults have become increasingly observable in combinational logic. This is due to the weakening of some inherent protective mechanisms that logic traditionally holds against such flawed spurious events. One of the aforementioned mechanisms relates to the propagation of transient faults along sensitizable paths. Existing literature that relies on logic simulation under estimates the number...
This paper describes an approach for analog-to-digital converter (ADC) linearity testing that can tolerate environmental nonstationarity and use low-precision test signals. The effects of stimulus errors on ADC testing results will be identified and removed by exploiting the functional relationship of input signals. The effects of environmental nonstationarity will be suppressed by interleaving input...
This paper deals with the specifications, characteristics, functions, and examples of applications of the Electronic Universal Load developed for use in the developement of power supply units, their testing and income inspection. The function of controlling load current by entering a BCD code permits, among other functions, automatic testing through connection to a computer. This paper gives a detailed...
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