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In Network on Chip (NoC), the number of cores get increases gradually in the past few decades. This affect the performance of the mesh and this leads to evolution of new topological concept. The king topology provides the high grade evolution of the humanistic mesh and torus topologies. This network exhibits a number of interesting characteristics which helps to achieve, reduced execution time of...
The transfer of big data in various applications across high-performance networks (HPNs) in a national or international scope consumes a significant amount of energy on a daily basis. However, most existing bandwidth scheduling algorithms only consider traditional objectives, such as data transfer time minimization, and very limited efforts have been devoted to energy efficiency in HPNs. In this paper,...
Due to potential heterogeneity in criticality of sensing data, machine-to-machine (M2M) networks are required to provide multi-level connectivity to the sink for device nodes. In this paper, topology control is discussed for M2M networks consisting of two different types of device nodes, called supernodes and ordinary nodes. Supernodes are required to have k node-disjoint paths to the sink while ordinary...
We consider the problem of minimizing the power consumption of Internet backbone networks by means of power aware design and auto configuration of Points of Presence (PoPs). We show that the problem of achieving a power-optimal PoP design under general traffic demands is NP-Hard. The problem is NP-Hard even when the traffic demands are correlated i.e. traffic demands across different source-destination...
The paper copes with the reduction of network power consumption by the definition of new routing algorithms, able to take into account the energy consumed by the network devices. In particular, based on the power consumption characterization of the network devices obtained using the Energy Profile (EP) concept, the paper presents the analysis of the exact solution of the Energy Aware Routing (EAR)...
The increasing viability of three dimensional (3D) silicon integration technology has opened new opportunities for chip design innovations, including the prospect of extending emerging systems-on-chip (SoC) design paradigms based on networks-on-chip (NoC) interconnection architectures to 3D chip designs. In this paper, we consider the problem of designing application-specific 3D-NoC architectures...
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