Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
Carry look-ahead adder (CLA) is a fast adder. This paper is delicated to accelerate the 4-bit CLA circuit. In proposed circuit structure, XOR gate is replaced by NOR gate. Moreover, logic gates have less fan-in and fan-out and signal throughs one less MOS transistor in critical path. All designs are built in dynamic CMOS logic gates. Simulation results show that the proposed architecture has advantages...
The design of high-performance adders has experienced a renewed interest in the last few years; among high performance schemes, parallel prefix adders constitute an important class. They require a logarithmic number of stages and are typically realized using AND-OR logic; moreover with the emergence of new device technologies based on majority logic, new and improved adder designs are possible. However,...
We present the first Verilog-A based models of a magneto-electric magnetic tunnel junction (ME-MTJ) based XNOR and NOR logic gates. The ME-MTJ is a low-power beyond-CMOS technology, with possible applications in memory and logic devices. The models presented here have been developed in Verilog-A and validated with simulations using cadence spectre. We show the operation of this ME-MTJ dual-purpose...
The increasing amount of circuit density possible in CMOS technology has the consequence of also increasing the power consumption of circuits using the technology. One possible method of offsetting these increased power demands is to use approximate computing designs in circuits where complete accuracy is not a strict requirement. These circuits use fewer logic gates which reduces power consumption...
Quantum-dot Cellular Automata (QCA) is a newly developed paradigm for digital design. It explains how computation can be performed using nano sized quantum dots. One of the trending application of QCA is the design of reversible logic circuits and gates. Reversible logic is a dissipation less digital logic. According to this logic digital circuitry with almost zero power dissipation can be designed...
Performance of adders has a tremendous impact on system-level functionality especially in signal processing applications. Carry Select Adder (CSLA) is one such adder which is proved to be a high speed version among other conventional adders. This paper presents a novel architecture for SQRT-CSLA with modified ripple carry adder chain. The pivotal feature of the proposed architecture is that the final-sum...
Memristors are non-volatile memory elements. In applications like mem-computing, where memory acts both as a site for storing data and logic computations, memristors provide promising future. In this paper, the design of adders implemented with memristors is discussed. Memristor based designs for standard fixed point adder architectures (ripple carry adder, carry look-ahead adder and parallel prefix...
Formal verification utilizing symbolic computer algebra has demonstrated the ability to formally verify large Galois field arithmetic circuits and basic architectures of integer arithmetic circuits. The technique models the circuit as Gröbner basis polynomials and reduces the polynomial equation of the circuit specification wrt. the polynomials model. However, during the Gröbner basis reduction, the...
A number system with radix-3 is referred to as Ternary system. With a lot of new ternary circuits being proposed as an alternative to the digital logic, we take a step further, in this paper we propose to design a Ternary coded Decimal (TCD) adder circuit based on CMOS technology. Unlike a Ternary adder, the TCD adder uses 3-bit Ternary coded Decimal (TCD) number as input and the resulting sum will...
The paper presents the design of a MAC unit that is based on the Vedic Square and its application, for the processing of equations that solely contain square terms. The use of Vedic Square as a replacement of the multiplier helps in reduction of area. In this paper, the Vedic Square is compared to the Vedic multiplier; both are based on the UrdhvaTiryagbhya sutra of Vedic mathematics. Duplex property...
Digital computations and calculations is involved in every embedded and processing device, these devices has arithmetic logic unit or a special block to perform a desired operation, Addition can be one such operation, adders are most important and fundamental block used for Addition, Subtraction, Multiplication, Division, Address generation and so on, design and selection of adders for a embedded...
Modulo (231-1) adder is one of the important module in ZUC stream cipher. The paper presents compact, high performance architecture for modulo (231-1) adder using CLA. The proposed architecture is implemented by using VHDL language with CAD tool Xilinx ISE Design Suite 13.2 and target device is Xilinx Spartan3-xc3s1000, with package FG320. Presented result shows that proposed architecture minimizes...
This paper presents a novel diagnosis and logic debugging method for gate-level arithmetic circuits. It detects logic bugs in a synthesized circuit caused by using a wrong gate ("gate replacement" error), which change the functionality of the circuit. The method is based on modeling the circuit in an algebraic domain and computing its algebraic "signature". The location and type...
Although a lot of effort has been spent on verifying arithmetic designs, it is still a problem that has no general robust automated solution. One major challenge is verifying large scale multiplier circuits. For this purpose, we revisit the idea of using functional properties of the multiplication function, which can be expressed by recurrence equations. Then, instead of proving the equivalence of...
This paper demonstrates the detailed design of carry look ahead adder with the single electron tunneling based threshold logic. Tunneling is a mechanism in which a single electron can cross a sandwiched structure of insulating layer between two conducting materials known as tunnel junction. The threshold logic works mainly on the basis of the comparison in between the threshold and the weighted sum...
This paper presents a unified logic for flagged prefix addition-subtraction that eliminates the need to perform constant addition and subtraction in two separate blocks. The logic is based on a modified algorithm for constant subtraction that allows us to achieve the unification which is not possible with traditional algorithms. Thus we are able to eliminate the most crucial challenge that practical...
This paper discusses modification to algorithms for computing within a parallel cubing unit. The algorithms discussed in this paper shows several architectures for various operand sizes ranging from 8 to 32 bits. The method proposed in this paper separates the cubing partial product matrix into smaller elements and organizes these partial products into repeatable manageable groups. Consequently, the...
The paper describes a method to derive a polynomial function computed by an arithmetic bit-level circuit. The circuit is modeled as a bit-level network composed of adders and logic gates and computation performed by the circuit is viewed as a flow of binary data through the network. The problem is cast as a Network Flow problem and solved using standard algebraic techniques. Extraction of the arithmetic...
Addition is a vital operation in all data paths. The power dissipation and speed performance remain the primary factors that identify the choice of adders. To achieve the desired energy efficiency or lower power dissipation, the selection of the particular adder topology plays a major role. The operating speed of adder or the circuit latency of adder can be minimized by the use of architectures such...
This paper presents a Reconfigurable Parallel Prefix Ling Adder. The proposed design can be partitioned to perform as one 16 bit, two 8 bit and four 4 bit adders. We also propose a new architecture for Enhanced Flagged Binary Adder (EFBA) designs which reduces the delay of operation considerably. The new adders are, therefore, modifications of conventional Reconfigurable Carry Lookahead Adder (CLA)...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.