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Some aspects should be considered in Nanoscale MOSFETS models, such as power dissipation, channel length modulation, and the overshooting effect. In this paper we study the impact of considering the overshooting effect in a previous nanoscale model, by including the subthreshold region where the overshooting effect appears. Results show a positive impact of modeling the overshooting effect on the...
Sub-threshold SRAM cells are attractive because of their low leakage power and low access energy. However, the susceptibility of sub-threshold SRAM cells to soft errors is high due to their low supply voltage, high density, and shrinking geometry. Moreover, the increase in statistical variations in advanced nanometer CMOS technologies poses a major challenge for sub-threshold circuits designers. In...
With the event of nanoscale technologies, new physical phenomena and technological limitations are increasing the process variability and its impact on circuit yield and performances. Like combinatory cells, the sequential cells also suffer of variations, impacting their timing characteristics. Regarding the timing behaviors, setup and hold time violation probabilities are increasing. This article...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
Current mode (CM) scheme provides suitable alternative for the high speed on-chip interconnect signaling. This paper presents a energy-delay optimization methodology for the current-mode (CM) signaling scheme. Optimization for the CM circuits for on-chip interconnects requires a joint optimization of driver and receiver device sizes, as their parameters which affect the energy-delay performance depend...
We present a generic method for analyzing the effect of process variability in nanoscale circuits. The proposed framework uses kernel and a generic tail probability estimator to eliminate the need for a-priori density choice for the nature of circuit variation. This allows capturing the true nature of the circuit variation from a few random samples of its observed responses. The data-driven, non-parametric,...
A novel methodology for accurate and efficient static timing analysis is presented in this paper. The methodology is based on finding a frequency domain model for the gates which allows uniform treatment of the gates and interconnects. It is shown that despite the highly nonlinear overall gate model, a frequency domain model of the gate with the model parameters, gate moments, as functions of the...
This paper presents an analytical modeling of ballistic and quasi-ballistic transport, implemented in Verilog-A environment and used for circuit simulation. Our model is based on the Lundstrompsilas approach and uses an expression of the backscattering coefficient given by the flux method. The model takes also into account short channel effects and tales into account the effects of different scattering...
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