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This paper presents some propositions to reduce consuming memory and increase operational frequency of hardware implementation of JPEG-LS algorithm for real time applications. By enhancement in the algorithm and using fast divider, memory has been reduced by 24%. Also, considering the proposed non-stalling pipeline architecture by using forwarding technique to avoid hazards, circuit frequency has...
Large register files are common in highly multi-threaded architectures such as GPUs. This paper presents a hybrid memory design that tightly integrates embedded DRAM into SRAM cells with a main application to reducing area and power consumption of multi-threaded register files. In the hybrid memory, each SRAM cell is augmented with multiple DRAM cells so that multiple bits can be stored in each cell...
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