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This paper examines the problem of generating testing actions for electronic industry test systems designed for verification of electronic packages of UHF band. This paper shows complex problems of setting amplitude and time parameters of multichannel generators of test signals. The problems of multichannel wide range signal generation and frequency control, rise and fall time control, pulse time...
Concept lattice is accurate and complete in knowledge representation and is an effective tool for data analysis and knowledge discovery. This paper focuses on classification rules mining based on concept lattices. By modifying incremental computation of intent reduction of concepts, it develops a method to mine affirmative classification rules and approximate classification rules using intent reduction.
A sine signal synchronous to the power system voltage signal is required in most power electronics based industrial applications. In this study, a phase locked loop (PLL) and direct look-up table (DLT) based hybrid sine oscillator is developed, and sinusoidal signals of the desired frequency that is synchronous to the reference input signal is generated in real time applications carried out with the...
In many distributed and pervasive systems the clocks of nodes are required to be synchronized to a unique global time. Due to unpredictable system and environment characteristics, the distance of a local clock from global time is a variable factor very hard to predict. Systems usually adopt measures to guarantee an upper bound on such distance from global time that are very often quite far from typical...
We propose QUEST (QUality ESTimation), a new method that accurately estimates IEEE 802.11 wireless link quality with no in-band signaling overhead. Existing link quality estimation methods either are based on hello exchanges by fixing or varying transmission rates or rely on the history (e.g., delivery ratio) of previously sent data packets in a per-rate/-neighbor manner. QUEST on the other hand,...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
A circuit for on-chip measurement of long-term jitter, period jitter, and clock skew, is demonstrated. The circuit uses a single latch and a voltage-controlled delay element, and is evaluated in a stand-alone pad frame. Excellent reproduction of jitter measured by oscilloscope is shown. Measured jitter resolution is 1 ps or better. The circuit is also incorporated into a 2 GHz clock distribution network...
A novel 50% duty-cycle corrector (DCC) of digital signal processing (DSP) systems, designed with a purely digital phase-blending technique, is presented in this paper. The novel features of the proposed DCC includes a higher reliability against process, voltage and temperature variation due to the use of the synchronous mirror delay (SMD) technique, no-skew output clock, and a much faster duty-cycle...
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