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The implementation of a digital four-level pulse-amplitude-modulation reduced-state sliding-block Viterbi detector (VD) with two substates and two embedded per-survivor decision-feedback taps operating at one-eighth of the modulation rate is described. Implemented in an experimental chip fabricated in 14nm CMOS, the VD is designed to recover data at 25.6 Gb/s over an emulated time-dispersive channel...
Signal acquisition systems for emerging applications, such as impiantatile or unobtrusively wearable autonomous sensors, large sensor arrays, or wireless self-powered sensors, require a minuscule form factor and very low power consumption. For example, the power available from a state-of-the-art 1mm3 solid-state thin-film battery is limited to 4nWfora 10yr lifetime [1], and a 1mm3 energy harvester...
The phased clock signals are useful to synchronize the individual modules within a multiphase digital system and satisfy the complexity of their clock timing requirement. The capability of the on-demand adjustment of the phased clocking pattern can be embedded to the circuit that generates the associated clocks by shifting in time their active clock edges. A delay insertion technique is presented...
In this work we present a low-power, low-area and high-speed fully CMOS quadrature clock generator for low-power and low-noise on-chip devices. The device is constructed around a couple of differential prescalers for high speed frequency division and four duty cycle adjusters to set the duty cycle of the produced clock signals at 50% of the clock period. The circuit was implemented with the STMicroelectronics...
There is a growing demand for high-performance, low-power systems, particularly in portable devices. New approaches to design are needed in technologies with feature sizes of 90 nm and below to reduce leakage power and to deal with process variations, which force designers to use increasingly conservative delay estimations. This paper presents a variable clock generator for a conventionally-designed...
In this paper, Sources of power consumption for CMOS logical circuits are analyzed and several BIST technologies of low power consumption are summarized. In order to reduce the switching activity rate of internal nodes in circuit-under-test and raise the correlation between testing vector, the Random Single Input Change (RSIC)test theory is introduced. It can reduce the switching activity rate of...
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