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With the advent of synchronous systems we have come across various difficulties and problems associated with them, mainly like clock skew, power consumption, etc. The idea of making systems clockless has been proposed numerous times and has been explored in great detail. Although we see that even those systems are not free from their own disadvantages like false triggering, handshaking hardware requirement,...
We propose an Asynchronous-to-Synchronous Interface Controller (A2S-IC) with low delay-variation towards Process, Voltage and Temperature (PVT) variations for sub-threshold/near-threshold operation in low power applications. This A2S-IC is targeted for a full-range Dynamic Voltage Scaling (DVS) Global-Asynchronous-Local-Synchronous (GALS) Network-on-Chip (NoC). There are three key attributes in this...
This paper proposes a 10 b 200 MS/s pipeline analog-to-digital convertor (ADC) for high-quality video systems based on double-channel and op-amp sharing schemes to minimize power consumption and channel mismatch. The double channel time-interleaved scheme reduces the required operating speed of amplifiers in the sample-and-hold amplifier and multiplying digital-to-analog (D/A) converters by 50%. The...
In this paper a Globally-Asynchronous Locally-Synchronous (GALS) pipelined processor is implemented on synchronous commercial FPGAs. A simple pipelined accumulator-based processor is implemented as an example for a pipelined processor with varying stages' delays. A novel port controller is designed to ensure the proper operation of the pipeline under any distribution of stage delays. The results show...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
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