The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Pre-scalar, this is considered as the most critical block in the design of frequency synthesis plays very important role, whenever we talk about high frequency operation. These blocks are used typically in PLLs for frequency synthesis. Rigorous experiments have proved that the major contribution for power dissipation in ADPLL is because of pre-scalar block. Hence it becomes very crucial to design...
An ultra-low voltage operation of 0.5 V, 5-bit Flash ADC has been developed and achieved an ENOB of 4.2-bit at a conversion rate of 600 MS/s. It consumes only 1.2 mW and attained an ultra-low FoM of 160 fJ/conv. steps at an ERBW of 200 MHz. A forward body bias technique and gate-interpolated double-tail latched comparator with variable delay method to compensate the mismatch voltage are introduced.
In this work a CMOS 1.2V 5GHz low-power voltage-controlled oscillator (VCO) is proposed. It uses an on-chip biased LC-tank topology and introduces a temperature compensation technique which stabilizes the oscillation amplitude for a robust I/Q generation using a frequency divider-by-2. Compared to a standard design with constant bias, it reduces the oscillation variation by almost two orders of magnitude...
In this paper, a CMOS analog-to-digital converter (ADC) for Ultra Wide Band (UWB) applications with a 6-bit 1GSPS at 1.8 V is described. The architecture of the proposed ADC is based on a fully folded ADC using resistive interpolation technique for low power consumption. To reduce the power consumption, a folder reduction technique to decrease the number of folding blocks (NFB) is proposed. Further,...
A high intercept points, cost-effective, and power-efficient switching FET double balanced mixer (DBM) is reported. The Switching FET DBM demonstrated in this work offers input intercept points (IIP3) and conversion loss typically 44 dBm and 8.5 dB respectively with 15 dBm LO power for the frequency band (RF: 900-2150 MHz, LO: 850-1950 MHz, IF: 50-200 MHz). The measured interport isolation is typically...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.