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In this work we propose and demonstrate the first active Nano-Electro-Mechanical (NEM) filters based on scaled vibrating body field effect transistor (VB-FET) with mechanically coupled flexural-mode beam resonators working at a fundamental resonant frequency of 115 MHz. The VB-FET filters are fabricated on a 200 nm thin SOI substrate using E-Beam lithography and sacrificial layer etching. Numerical...
PVD-TiN gate FinFET SRAM half-cells with different β-ratios and fin-height controlled transistors have successfully been fabricated using orientation-dependent wet etching and selective recess RIE. It was found that read static noise margin (SNM) increases significantly by controlling β from 1 to 2. With further increasing β, read SNM increases slightly. On the other hand, write margin shows weak...
Foreseen operation at sub-THz frequencies of Schottky contacts for diodes and transistor gates on GaAs based heterostructures requires area reduction down to 0.1×1 microns, and wet chemical processes. We report on the compatibility of Trilayer Electron-beam Lithography with such wet processes.
Here we report on top-contact organic TFTs and complementary circuits fabricated using stencil masks with a resolution of 1 μm. The stencil masks were manufactured on silicon-on-insulator (SOI) wafers, with the buried SiO2 serving as an etch stop during the formation and patterning of the Si membrane, which has a thickness of 20 μm [10,11]. Openings in the Si membrane were created by electron-beam...
In this paper, we demonstrate a self-aligned gate-first process for fabrication of T-gates without much degradation of fτ. The device layer structure is shown. The fabrication process involves formation of W/Cr gates using a self-aligned gate-etch process similar to the InGaAs MOSFET technology reported by Rodwell et. al. [2008, 2009]. After formation of a 130 nm long gates, graded InGaN/InN-based...
Direct patterning of silicon dioxide by electron beam lithography is used for the definition of metal nanojunction on wires fabricated on silicon on insulator (SOI) substrates. Devices based on a single silicon nanowire as small as 15 nm and several micrometers long are fabricated by means of a top down process based on electron beam lithography, silicon anisotropic etching and thermal oxidation....
We developed a new technology that reduces gate length with modified sloped etch process to fabricate nanometer scale high-electron mobility transistors (HEMTs). The polymer deposition and Si3N4 etching with positive slope make this technology realizable. A HEMT with this technology has merits of both fine length definition beyond the limit of an electron beam (E-beam) lithography system and overcoming...
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