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Convolutional neural networks (CNNs) are revolutionizing machine learning, but they present significant computational challenges. Recently, many FPGA-based accelerators have been proposed to improve the performance and efficiency of CNNs. Current approaches construct a single processor that computes the CNN layers one at a time; the processor is optimized to maximize the throughput at which the collection...
This paper presents an efficient design method used to implement high performance multi-mode memory controllers which fits different applications with different demands. The proposed design method is based on the use of dynamic partial reconfiguration (DPR) to commute from mode to another using time-multiplexing on the same chip region to save considerable area and enable usage of low-cost FPGAs....
Application specific integrated circuits (ASICs) are commonly used to implement high-performance signal-processing systems for high-volume applications, but their high development costs and inflexible nature make ASICs inappropriate for algorithm development and low-volume DoD applications. In addition, the intellectual property (IP) embedded in the ASIC is at risk when fabricated in an untrusted...
Deep neural networks have gained tremendous attention in both the academic and industrial communities due to their performance in many artificial intelligence applications, particularly in computer vision. However, these algorithms are known to be computationally very demanding for both scoring and model learning applications. State-of-the-art recognition models use tens of millions of parameters...
The transmission speed of mobile communication systems for mobile and IoT (Internet of things) devices is getting faster. Advanced, high-speed and low-power processing on network packets are needed in these devices. To realize these performances in the devices, the authors have proposed FPGAs (field-programmable gate arrays) which are developed by the RTL (register-transfer level) design methodology...
Bus Administrator capability is the key characteristic of MVB Class 4 Device, which is the main equipment in the MVB network. A novel MVB Bus Administrator Controller design method based on the SOPC technology is presented, which each function is realized by the Nios II application software. Finally, the performance of the Bus Administrator is evaluated in the TCN hardware-in-loop simulation platform...
This paper presents the design methodology of a complete digital pre-distortion system that enables the power amplifier linearization. This system employs the memory polynomial model for its realization. The performance of the linearization is validated by using an LTE carrier signal in the band of 10 MHz. This integrated solution is capable of linearizing any real power amplifier from measurements...
Modern system-on-chip designs are characterized by their high complexity. It results in an increased number of transistors in a single chip, size of which is continuously decreasing due to market requirements. These issues have negative impact on reliability of the system, mainly because of the overheating of the device due to its power requirements. The result is that designers have to implement...
Convolutional Neural Networks (CNNs) are a variation of feed-forward Neural Networks inspired by the biological process in the visual cortex of animals. The interest in this supervised learning algorithm has rapidly grown in many fields like image and video recognition and natural language processing. Nowadays they have become the state of the art in various applications like mobile robot vision,...
Field-programmable gate arrays (FPGAs) are used in various systems that use reconfigurable function. Conventional FPGAs have been developed by a transistor-level description for minimizing routing delay. Although FPGAs developed by the register transfer level (RTL) design methodology provide various benefits to the designers of a system-on-a-chip (SoC), they have not been realized. Therefore, the...
The paper is concerned with the modern methodologies for holistic modelling of electronic systems enabling system-on-chip design. The method deals with the functional modelling of complete electronic systems using the behavioral features of Hardware Description Languages or high level languages then targeting programmable devices — mainly Field Programmable Gate Arrays (FPGAs) — for the rapid prototyping...
A design method is proposed for FPGA-based Moore FSMs. The method is based on presentation of state codes as concatenations of codes of classes of pseudoequivalent states and collections of output functions. Examples of design and results of investigations are given. The method allows obtaining FSM logic circuits having less amount of LUTs than known from literature methods.
A design method is proposed for LUT-based Mealy FSMs. The method is based on transformation of collections of output functions into state variables. Example of design and results of investigations are given. The method allows obtaining FSM logic circuits with less amount of LUTs than known from literature methods.
Laboratories and project work are widely used in the engineering curricula around the world. Such hands-on trainings allow the students to learn hard-as well as soft-skills and can be used to prepare them for the work in the industry. In microelectronics education laboratories are often offered. For such a laboratory the authors present a set-up to teach microelectronic design using a top-down design...
Nowadays, image and video processing applications are becoming widely used in many domains including industrials, medical imaging, manufacturing, and security systems. Real time image and video processing is a very demanding task as it needs to perform high computations for a big amount of data represented by the image, and the complex operations, which may need to be performed on the image. For these...
Reconfigurable analog/mixed signal (AMS) platforms in scaled CMOS technology nodes are gaining importance due to the increased design cost, effort and shrinking time-to-market. Similar to field programmable gate arrays (FPGA) for digital designs, a Programmable ANalog Device Array (PANDA) provides a flexible and versatile solution with transistor-level granularity and reconfiguration capability for...
Embedded systems (ES) based on field programmable gate arrays (FPGAs) enhance the overall computational capability and relieve computational load. The lack on design and implementation methods for specific control functions in hardware limits the application of complex control techniques. Therefore, a design methodology approach is showed in the current work. Fuzzy, LQR, and PI control systems are...
Advances in integrated circuit technology are enabling construction of increasingly more powerful architectures for Software Defined Radio (SDR) platforms. For instance multicores, multiprocessor System-on-Chip and FPGAs provide opportunities for innovative prototyping and increased programmability whereby more radio processing is done in the digital domain. But there are challenges with these technologies,...
This paper presents a review of the state of the art of the design methodologies for Hardware (HW) and Software (SW) for design of the digital control system in power electronic converters. This paper presents also a review of programmable electronic devices used in applications including power converters: Microcontroller (μC), Digital Signal Controllers (DSC), Digital Signal Processors (DSP) and...
This paper presents two design methodologies for hardware/software (HW/SW) architectures. The first one uses High Level Synthesis (HLS) based on Catapult C Synthesis. From C++ descriptions, this design flow is able to automatically produce hardware blocks that can fully operate with CPU cores on Xilinx prototyping platforms (FPGA). The second methodology relies on a manual RTL (Register Transfer Level)...
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