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As CMOS continues to approach the physical limits of silicon, interest has greatly increased in the use of high mobility alternatives for devices beyond the 14 nm technology node. By virtue of their high electron and hole mobilities, InGaAs and Ge respectively have emerged as the most promising candidates for n- and p-MOS but the co-integration of these materials on the same Si wafer remains a significant...
We are introducing an innovative sacrificial surface micromachining process that enhances the robustness of freestanding microstructures and compliant mechanisms. Fabrication of a compliant mechanism using conventional sacrificial surface micromachining results in a non-planar structure with a step between the structure and its anchor. During mechanism actuation or assembly, stress accumulation at...
Two types of solar cells are successfully grown on chips from two CMOS generations. The efficiency of amorphous-silicon (a-Si) solar cells reaches 5.2%, copper-indium-gallium-selenide (CIGS) cells 7.1%. CMOS functionality is unaffected. The main integration issues: adhesion, surface topography, metal ion contamination, process temperature, and mechanical stress can be resolved while maintaining standard...
A surface-micromachined capacitive-type micro-electro-mechanical system (MEMS) acoustic sensor with X-shape bottom electrode anchor on a Si substrate is presented. As it is designed to be implemented on only one side of a substrate for a simple monolithic integrated process, this sensor has X-shape bottom electrode anchor fabricated. The anchor operates to remove the back side process of wafer for...
This paper describes several methodologies based on a pulsed laser beam to reveal the architecture of a high integrated SDRAM, and the different classes of Single Event Effects that can occur due to cosmic radiations. At cell level, laser is used to reveal an important technological parameter: the lithography process. At memory array level, laser is a powerful tool to retrieve cell physical arrangements,...
For several decades, the output from semiconductor manufacturers has been high volume products with process optimisation being continued throughout the lifetime of the product to ensure a satisfactory yield. However, product lifetimes are continually shrinking to keep pace with market demands. Furthermore there is an increase in dasiafoundrypsila business where product volumes are low; consequently...
This work aims to examine and analyze carefully the effects of block oxide length (LBO) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-aligned (SA) gate-to-body technique. In the MSCFET design the two key parameters are the length and the height of the block oxide which are so sensitive to the short-channel effects (SCEs)...
This paper presents an innovative structure based on 3 dimensional integration technology, where ultra thin inter layer dielectric enables a dynamic threshold voltage (VTH) control. A sequential process flow is proposed to fabricate 3D devices with dynamically tunable VTH. This ability can be exploited to design SRAMs cells with increased stability and surface density compared to planar technology...
Novel 3D stacked gate-all-around multichannel CMOS architectures were developed to propose low leakage solutions and new design opportunities for sub-32 nm nodes. Those architectures offer specific advantages compared to other planar or non planar CMOS devices. In particular, ultra-low IOFF (< 20 pA/mum) and high ION (> 2.2 mA/mum) were demonstrated. Moreover, those transistors do not suffer...
Advances in micromachining technology can facilitate the integration of SAW (Surface Acoustic Wave) devices and CMOS circuitry on IC scale substrate for Monolithic fabrication. The optimal design and performance of these filters can be reached by using new Smart materials. The key component in the structure of the SAW device is the piezoelectric materials used which depends mainly on some important...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
We have observed new charge trapping phenomena in sub-80-nm DRAM recessed- channel-array-transistor (RCAT) after Fowler-Nordheim (FN) stress. Gate stack process strongly affected the charge trapping and the trap generating in oxide bulk and interface of RCAT. According to the trapped charges and/or the generated traps after FN stress, the data retention time and writing capabilities of DRAM were dramatically...
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