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A health monitoring method using the saturationregion resistance is proposed in this paper to identify the level of aging associated with power semiconductor switches inside a Boost converter. Power MOSFETs are one of the most age-affected components in power electronic converters, and the on-resistance has been proved to be the most significant aging factor in power MOSFETs. However, the small value...
Short-circuit detection is one important feature of a gate-drive unit and a solution without a collector sense is preferable. With monitoring the gate-emitter voltage, a short can be easily detected. A circuit, which detects and turns off the short, and measurements for different shorts on high-voltage IGBTs are presented.
Power MOSFET plays an important role in power electronic systems, the failure of which will lead to system losing functions. Thus the degradation failure process and mechanism of MOSFET attract wide attention of scholars. However current research works cannot solve the real time degradation monitoring problem of MOSFET. Normally, MOSFET should be removed from the system for testing or monitoring....
A Photovoltaic (PV) system needs to monitor individual PV panels to maintain the performance. In a high-dense large-scale PV system, two characteristics can limit the use of communication technology. First, high density can degrade wireless communication performance due to the interference between densely deployed nodes. Second, a large-scale area can limit the communication distance in power line...
Wireless Sensor Networks have highly been in demand in the recent times for monitoring and controlling purposes. Low cost, low power and simpler architecture involving the wireless sensor modules have made them quite an acceptable tool for data monitoring. But interference has been the major area of concern in WSN which often leads to data loss during data monitoring and have immense ill-effects in...
In this paper, we propose a kind of novel energy-efficient programming approach for microcontroller units which helps to minimize processing power costs of any self-sustainable sensor device. This approach is based on an event driven programming principle taking advantage of flag-based logic. The framework called Entity Dust Container (EDC) was introduced for this purpose. Significant power savings...
A novel procedure for voltage standing wave ratio (VSWR) ruggedness testing of GaN-HEMTs is described. In the test the transistor is exposed to an increasing level of VSWR stress and an extensive set of marker parameters are monitored before, during, and after stress. A gate- and drain-lag pulse response test has been developed that reveals VSWR stress influence on slow surface charges. Recovery is...
A novel procedure for voltage standing wave ratio (VSWR) ruggedness testing of GaN-HEMTs is described. In the test the transistor is exposed to an increasing level of VSWR stress and an extensive set of marker parameters are monitored before, during, and after stress. A gate- and drain-lag pulse response test has been developed that reveals VSWR stress influence on slow surface charges. Recovery is...
We propose a maximum power point tracking (MPPT) circuit for micro-scale sensor systems that measures ripple voltages in a switched capacitor energy harvester. Compared to conventional current mirror type MPPT circuits, this design incurs no voltage drop and does not require high bandwidth amplifiers. Using correlated double sampling, high accuracy is achieved with a power overhead of 5%, even at...
Design techniques for realizing analog switch and rail-to-rail constant gm opamp with approximately twice the standard supply voltages and signal swings are proposed in this paper. Based on these techniques, a 6 V stimulation monitoring circuit for monitoring 8 different stimulator outputs was implemented in a conventional 0.18 mum CMOS process using standard 3.3 V I/O devices. Maximum on-resistance...
Overshoot voltages during VFTLP testing of DTSCRs are investigated. The DTSCRs in a 65 nm process turn on at approximately 500 ps. The overshoot voltages from DTSCRs are shown to cause gate oxide failures when gate oxide monitors were added in parallel to DTSCR ESD devices. Scaling trends show DTSCRs turning on at approximately 150 ps when technologies are scaled down to the 32 nm node.
The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm CMOS technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate...
Timing-error detection and recovery circuits are implemented in a 65 nm resilient circuit test-chip to eliminate the clock frequency guardband from dynamic supply voltage (VCC) and temperature variations as well as to exploit path-activation probabilities for maximizing throughput. Two error-detection sequential (EDS) circuits are introduced to preserve the timing-error detection capability of previous...
Since the very beginning of the flash memory era, the market has been dominated by the floating gate technology. However, as floating gate flash continues along a very steep scaling path, more and more barriers start to appear, limiting further scaling possibilities of the technology. At the same time, other concepts are preparing to take over. This paper concentrates on the prospect of high-k materials...
A high bandwidth critical path monitor (1 sample/ cycle at 4-5 GHz) capable of providing real-time timing margin information to a variable voltage/frequency scaling control loop is described. The critical path monitor tracks the critical path delay to within 1 FO2 inverter delay with a standard deviation less than 3 FO2 delays over process, voltage, temperature, and workload. The CPM is sensitive...
Simple ring-oscillator circuit has been used to estimate the degradation in circuit performance due to negative bias temperature instability (NBTI) effect but it fails to isolate the degradation from the NBTI for PMOS and the positive bias temperature instability (PBTI) for NMOS in high-K dielectric/metal gate CMOS technology. In this paper, we propose new circuit structures which monitor the NBTI...
Plasma-exposed Si surface related to Si recess in source/drain region was investigated in detail for various superposed bias configurations with frequencies of 13.56 MHz and 400 kHz. Two different bias powers were utilized by an inductively coupled plasma reactor (ICP). The surface layer (SL) and the interfacial layer between the SL and Si substrate (IL) were analyzed by spectroscopic ellipsometry...
In order to guide the design and improvement of grading and shielding rings to meet the requirements of UHV projects in China, research on corona characteristics of these components is needed. One of the difficulties is that there is a lack of a proper definition of visible corona. It is common using visual observation, which is easily effected by subjectivity and the observation background. In this...
In deep submicron era, to prevent larger amount of SRAM from more frequently encountered overheating problems and react accordingly for each possible hotspots, multiple ideal run-time temperature sensors must be closely located and response rapidly to secure system reliability while maintaining core frequency. This paper presented a method to extract run-time temperature information from multiple...
An extension of the conventional static CV procedure is presented which explicitely monitors the equilibrium of MOS capacitors throughout the CV sweep. Simultaneously to the static capacitance the minority carrier generation current is deduced by analyzing the time dependent displacement charge.
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