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We fabricated 〈100〉, 〈110〉, 〈111〉, and 〈112〉 p-channel gate-all-around Si nanowire (SiNW) MOSFETs, cross sections of which are rectangles with various widths, and investigated the hole mobility of the SiNW MOSFETs using the double Lm method. Measured hole mobilities of SiNW MOSFETs were about 80–140 cm2/Vs at surface carrier density of 1 × 1013 cm−2. The dependences of the hole mobility on orientations...
The impact of nanowire (NW) height and Si0.7Ge0.3:B source-drain (S/D) on the performance of p-type trigate NW is presented. We show that an increase in Si NW height from 14.5nm to 24nm generates up to +30% enhancement in hole effective mobility for a 13nm NW width. Effectiveness of Sio.7Geo.3:B S/D is then discussed for a wide range of NW width (13nm<W<218nm) and height (11nm<HNw<24nm)...
Hole mobility in ultra-thin body (UTB) InSb-OI devices is calculated by a microscopic approach. An adaptive grid algorithm is employed to discretize 2-D k space. The accurate valence band structures are obtained via solving the 6-band k·p Schrödinger and Poisson equations self-consistently. Hole mobility is computed using the Kubo-Greenwood formalism accounting for nonpolar acoustic and optical phonons,...
We have systematically investigated Ge interface passivation methods, and the highest electron (1920 cm2/Vs) and hole mobility (725 cm2/Vs) have been demonstrated by dramatic reduction of Dit through the collaboration of self-passivation and valency passivation. In Si passivation, it is found that Si contributes to the upper half (worse) and lower one (better) in the bandgap differently. This study...
P-MOSFETs with HfO2 gate dielectric and TiN metal gate were fabricated on compressively strained SiGe layers with a Ge content of 50 at.% and electrically characterized. The devices showed good output and transfer characteristics. The hole mobility, extracted by a split C-V technique, presents a value of ~200 cm2/V·s in the strong inversion regime.
Ultrathin (11 nm) strained SiGe-on-insulator (SGOI) with a Ge fraction of 0.5 was fabricated by Ge condensation technique. The residual compressive strain as high as 1.72% was achieved in SGOI layer by reducing the initial thickness of as-grown Si0.93Ge0.07 layer. Strained-SGOI pMOSFET exhibits a hole mobility of 3 times higher than that of Si-on-insulator pMOSFET.
In this paper, electron mobility (μ<;sub>e<;/sub>) and hole mobility (μ<;sub>h<;/sub>) of (110) nFETs and pFETs are studied, respectively. It is demonstrated that, because of the non-parabolicity along <;110>, the conventional effective mass model is insufficient to accurately evaluate the quantum confinement effects in (110) nFETs..
Continuously down-scaling EOT and improving mobility are required for CMOS device. Small 0.6~1 nm EOT and low Vt of ~0.15 V are achieved in CMOS by using higher κ gate dielectric and novel process. The ultimate EOT scaling is limited by the inserted ultra-thin SiON interfacial layer in high-κ/Si to reduce the mobility degradation. Further mobility improvement is obtained by using Ge channel MOSFET...
Integration of lanthanum lutetium oxide (LaLuO3) with a κ value of 30 is demonstrated on high mobility biaxially tensile strained Si (sSi) and compressively strained SiGe for fully depleted n/p-MOSFETs as a gate dielectric. N-MOSFETs on sSi fabricated with a full replacement gate process indicated very good electrical performance with steep subthreshold slopes of ~72 mV/dec and Ion/Ioff ratios up...
Hole mobility in fully-depleted GeOI pMOSFETs is determined and analyzed using for the first time the geometric magnetoresistance technique. The temperature dependent measurements clarify the scattering mechanisms. A significant difference between effective mobility and magnetoresistance mobility is found. Unlike the SOI nMOSFET, this ratio (rMR ≃ 1.8) is rather independent on the temperature and...
Systematic study has been performed on carrier mobility in sub-10nm gate-all-around (GAA) Si nanowire (NW) FETs on (100) SOI. The NW height is 4 - 10nm and the minimum NW width is shrunk to 5nm. For the first time, higher hole mobility than universal mobility is experimentally observed in 9nm-wide NW and even in 5nm-wide NW, demonstrating great advantage of NW pFETs, while electron mobility degradation...
We present the shortest and narrowest high-κ/metal gate n- and pFETs on compressively strained enriched SiGe On Insulator (c-SGOI) reported to date (LG=20nm; W=30nm; TSiGe=15nm). The range of active area widths in this work allows observing the transition from biaxial to uniaxial stress due to lateral elastic strain relaxation, and its benefit down to 20nm gate length on hole mobility and pFET performance...
Hole mobility in high Ge-content SiGe inversion layer is measured and simulated by a split C-V method and a quantized k.p method, respectively. For an arbitrary crystallographic surface orientation the two dimensional hole gas subband structure is calculated by solving the 6 ?? 6 k.p Schrodinger equation self-consistently with the electrostatic potential. Three important scattering mechanisms are...
We have developed a ballistic self-consistent code which couples the six-band k.p Hamiltonian to the Green function formalism. We investigate the influence of channel material (Si, Ge, SiGe and GaAs), crystallographic orientation ([100] and [110]) and strain (biaxial and uniaxial) on the ultimate double-gate pMOSFET performances. The results show that the best configuration is obtained with strained...
This study combines direct measurements of channel strain, electrical mobility measurements and a rigorous modeling approach to provide insight about the strain induced mobility enhancement in FinFETs and guidelines for the device optimization. Good agreement between simulated and measured mobility is obtained using strain components measured directly at device level by a novel technique. A large...
We report on the promise of dual channel materials using FinFETs for high-performance CMOS for sub 22 nm technology node. We demonstrate pFinFETs with all SiGe channel formed by Germanium condensation onto a Silicon-On-Insulator carrier wafer (SiGeOI) followed by cMOS processing. The devices exhibit 3.6X hole mobility enhancement over Silicon (100) while allowing for VTH control with single high-k...
Ge/Si core/shell gate-all-round nanowire pMOSFET integrated with HfO2/TaN gate stack is demonstrated using fully CMOS compatible process. Devices with 100 nm gate length achieved high ION of ~946 ??A/??m at VG - VT = -0.7 V and VDS = -1 V and on/off ratio of 104 with decent subthreshold behavior. Significant improvement in hole mobility and ballistic efficiency is demonstrated as a result of core/shell...
In this paper, deep amorphization of SOI substrate that preserves a crystalline surface layer was demonstrated on (110) and (100) oriented SOI films. The crystalline integrity of the surface layer allowed it to be a template for solid phase epitaxy. At an optimized temperature, pseudo-MOSFET measurements indicate a complete recovery of the electronic properties. However, a small increase is observed...
Compressively-strained germanium-on-insulator (c-GeOI) substrates have been fabricated using the Smart Cuttrade technology. The technique is based on the optimized epitaxial growth process that reduces the threading dislocation density (TDD) in the strained Ge layer to the levels of 8middot105 /cm2. Pseudo-MOSFET characterization showed 67% hole mobility enhancement with respect to conventional GeOI...
In this research, holes mobility enhancement is studied using Silicon Germanium, SiGe technology. SiGe is deposited on silicon substrate to increase carrier mobility in the device thus will increase the drive current too. The main focus of the research is to investigate the effect of using SiGe on holes mobility. In addition, variation thicknesses of SiGe on device characteristic are also studied...
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