The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
With the expansion of the scale of wireless sensor network (WSN), the network node number is increasing. Because of the huge network overhead and low precision, the reference broadcast time synchronization algorithm can not meet the actual demand. In this paper, a novel time synchronization algorithm for high precision energy efficient wireless sensor networks is proposed. Through a Markov random...
Enhancing observability is a key challenge in post-silicon validation. On-chip trace buffers store real time data which can be used for analyzing and debugging. Appropriate selection of these signals is crucial for storing useful debug data. This paper proposes a methodology for identifying trace signals so as to maximize detection of erroneous behavior of the failing chip which helps in improving...
Today, the design of complex synchronous digital systems shows serious difficulties relating to the global clock and to Deep-Sub-Micron MOS technology. The asynchronous design is an interesting alternative to solve these difficulties, once they do not present clock skew or distribution problems. However, the lack of tools for automatic synthesis is still a major drawback. Asynchronous Finite State...
Multiple-input multiple-output (MIMO) radar can achieve improved localization performance by employing a coherent processing approach with proper antenna positioning. Different from the noncoherent counterpart, coherent processing entails the challenge of ensuring phase coherence of the carrier signals from different distributed radar elements. In this paper, we propose a broadcast consensus based...
Speed-limiting paths are critical paths that limit the performance of one or more silicon chips. This paper present a data mining methodology for analyzing speed-limiting paths extracted from AC delay test measurements. Based on data collected on 15 packaged silicon units of a four-core microprocessor design, we show that the proposed methodology can efficiently discovered actionable, design-related...
The standard approach to the Backtracking Algorithm is to use any programming language and code that in a sequential manner. The work describes the implementation of a fast computation of the Backtracking Algorithm with FPGA (Field Programmable Gate Array) logic. The specific problem is then encoded into the FPGA structure and solved in the hardware. Each partial candidate of the solution is then...
In this paper, we have proposed a permission based distributed mutual exclusion algorithm which is an improvement of Maekawa's algorithm. The number of messages required by the improvised algorithm is in the range 3M to 5M per critical section invocation where M is the number of intersection nodes1 in the system. A reduction in number of message by restricting the communication of any node with the...
The decisions on when to acquire debug data during post-silicon validation are determined by trigger events that are programmed into on-chip trigger units. In this paper, we investigate how to design trigger units that are both resource-efficient and runtime programmable. To achieve these two goals, we introduce new architectural features, as well as an algorithm for automatically mapping trigger...
We present two designs (I and II) for IEEE 754 double precision floating point matrix multiplication, an important kernel in many tile-based BLAS algorithms, optimized for implementation on high-end FPGAs. The designs, both based on the rank-1 update scheme, can handle arbitrary matrix sizes, and are able to sustain their peak performance except during an initial latency period. Through these designs,...
The Niagara2 CMT system-on-chip incorporates many design-for-test features to achieve high test coverage for both arrays and logic. All the arrays are tested using memory built-in-self-test. This is supplemented with scan-based testing. Logic is tested with standard ATPG for slow-speed defects and extensive use of transition test, along with logic built-in-self-test for the SPARC cores, for at-speed...
While the CMOS analog circuits can be designed with the minimum-gate-length of the fabrication process in the alpha-power law MOSFET model, the length of a MOSFET gate has been chosen to be a larger scale than the minimum-gate-length in the conventional Shockleypsilas square model. In this paper, we describe a 6-b 100 MSPS CMOS current steering digital-to-analog converter (DAC) with the alpha-power...
This paper studies efficient complex valued matrix manipulations for multi-user STBC-MIMO decoding. A novel method called Alamouti blockwise analytical matrix inversion (ABAMI) is proposed for the inversion of large complex matrices that are based on Alamouti sub-blocks. Another method using a variant of Givens rotation is proposed for fast QR decomposition of this kind of matrices. Our solutions...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.