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In this paper we propose a hardware reduction methodology through detailed algorithmic analysis and exploiting datapath symmetry for 2D Kurtotic Fast ICA. The relationship of the hardware saving with respect to input data frame-length and maximum iteration for convergence is also explored. An example architecture following the developed hardware reduction methodology consumes 3:55 mm2 silicon area...
Fixed-point VLSI architecture for 2-Dimensional Kurtotic FastICA with reduced and optimized arithmetic units, is proposed. This reduction is achieved through the removal of the dividers for eigenvector computation and replacing the dividers in the Whitening block of the architecture by multipliers. In addition, the number of multipliers required in the Whitening block is further reduced by exploiting...
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