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This paper presents the authors' research work in the fields of embedded real-time softcore systems on FPGAs and specialized optimizing assembly language compiler. With this softcore processor, we are targeting a highly specialized field of applications that require a large floating point precision and other unique characteristics. Therefore, a specialized optimizing assembly language compiler is...
In this paper, a custom software defined radio that implements a smart antenna array is used in the task of real-time beamforming. Specific beamforming algorithms are implemented in FPGA, remotely controlled by a computer host. The antenna array is mounted in a metallic cylinder and tested in anechoic chamber. Experimental measurements highlight the efficiency of the algorithms implementation. Moreover,...
The paper is devoted to the implementation on the FPGA of the algorithm for the optimal combining of signals. Described the algorithm, the architecture of the optimal combining block, implemented to a four-element antenna system. The signal-to-noise ratio chosen as a criterion reflecting the efficiency of interference suppression in the reception band (increase of noise immunity). The effectiveness...
The paper presents an implementation of the Goertzel algorithm in FPGA (Field Programmable Gate Array) logic as a proposed algorithm utilized in Eddy current NDT (Non-Destructive Testing) instrumentation equipment. The FPGA running a real-time Goertzel algorithm in Eddy current NDT application is a novel approach different from the usual methods; such are the quadrature demodulation and discrete FFT...
In Cooley-Tukey algorithm the Radix-2 decimation-in-time Fast Fourier Transform is the easiest form. The Fast Fourier Transform is the mostly used in digital signal processing algorithms. Discrete Fourier Transform (DFT) is computing by the FFT. DFT is used to convert a time domain signal into its frequency spectrum domain. FFT algorithm use many applications for example, OFDM, Noise reduction, Digital...
This paper presents an FPGA-based prototype of the dual link algorithm that maximize the achievable weighted sum rate for MIMO interference network. The iterative algorithm is fast monotone convergent but it must be completed quickly through pilot signaling. Therefore we propose an FPGA-based implementation, targeting software defined radio (SDR) platforms, that is designed to rapidly process the...
This paper introduces a new FPGA architecture optimized for Frequency Modulated Continuous Wave (FMCW) Synthetic Aperture Radar (SAR). The architecture implements a Global-Backprojection-Algorithm (GBP) which has been modified to be independent of platform velocity (start-stop-approximation). The design supports parallelism of dedicated GBP processing modules in order to provide high performance....
For a charging process of an electric vehicle it is important that the process runs safely from the view of the electric site. For this reason in this paper advanced electronic circuit breaker techniques are presented, optimised for the use in electric vehicle charging stations. In doing so the focus lies on the continuous monitoring of the charging process related to the temporal course of the voltage...
Security plays a major role in the world of e-commerce. Cryptography is important for effective secure communication. The low-resource devices in the market needs lightweight ciphers for the hidden writing. In this paper a detailed study of HIGHT cryptographic algorithm is done. HIGHT is an ISO Standard block cipher which has 64-bit block length and 128-bit key length. HIGHT was designed to be proper...
Intra prediction algorithm in the recently developed High Efficiency Video Coding (HEVC) standard has very high computational complexity. High-level synthesis (HLS) tools are started to be successfully used for FPGA implementations of digital signal processing algorithms. Therefore, in this paper, the first FPGA implementation of HEVC intra prediction algorithm using a HLS tool in the literature is...
Ultrasonic NDE and imaging applications utilize a large amount of information. Most of these applications demand real-time data processing with low power consumption. Compression of the collected ultrasonic data helps to reduce the storage, as well as rapid data transmission to remote locations for expert analysis. The objective of this study is to develop embedded system-on-chip architectures for...
Optical Character Recognition (OCR) is an important area of pattern recognition. Automatic OCR system is one kind of intelligent system which is very important to the current automation systems such as ATMs. In this paper, a RMB OCR (ROCR) system is implemented using FPGA, which consists of Character Segmentation (CS) module and OCR module. The CME M7 was used for the implementation. 83.30% Logic...
Stable output level increases the accuracy of further signal processing algorithms. So, gain control algorithms are important pre-processing steps. On the other hand, implementation of gain control algorithms vary depending on environment and performance parameters. In this case, the algorithms are required re-implementation. Reimplementation is a time consuming process especially for embedded signal...
As floating point architecture is very hot topic for researchers so challenges are always there to design the efficient Floating point architecture. Out of other operations, Floating point multiplication is the most commonly used operation and it requires the multiplication of the mantissa of Floating point numbers. This paper presents the highly efficient 64 bit multiplier for the mantissa calculation...
This paper bring a description of ‘HSCoT’, an efficient high level synthesis tool generating register transfer level (RTL) specifications for applications written entirely in C language and an associate reliable approach for speeding applications execution. It's based on dependency data flow graph construction and aims to explore maximally the inherent intrinsic parallelism of application. Application...
The EEG pre-processing steps involve removing noise and artifacts from EEG. The noise from the main source like electro-oculogram, electrocardiogram, electromyogram and other sources should be eliminated to increase accuracy in classification. As these artifacts may be misinterpreted as originating from the brain, there is a need to minimize or remove them from recorded EEG signals. The artifacts...
The quest for faster and power efficient algorithms has necessiated the need for faster and power efficient multipliers since multiplication is used frequently. Often, the numbers to be multiplied are quite large. The multiplication method proposed in this work, Nikhilam sutra or algorithm, is derived from the ancient Indian texts known as Vedas. Elliptic curve cryptography (ECC) involves repeated...
This work describes a way to optimize the controller fixed-point representation in programmable logic devices (eg. FPGA) with genetic algorithms. The optimization uses the error between floating-point and fixed-point representation as well as a quantization noise error model. Thus, both terms allow weighting between the to be expected theoretical and actually occurred simulation error. This task could...
To improve the signal to noise ratio in the auto-tracking receiver, the traditional two dimensional acquisition algorithm is often used. However, its application has been limited because of the large amount of calculations. In this paper, a low-complexity cross-correlation algorithm is proposed. Firstly, the theoretical deviation is given. And then its implementation based on Field Programmable Gate...
The newly introduced Kubelka-Munk Genetic Algorithm (KMGA) is a promising technique used in the assessment of skin lesions. Unfortunately, this method is computationally expensive due to its function inverting process. In the work of this paper, we design a Predictive Function Optimization Algorithm in order to improve the efficiency of KMGA by speeding up its convergence rate. Using this approach,...
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