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A high-throughput architecture of the CCSDS 122.0-B-1 image compression standard is proposed. The architecture uses a novel memory organization in order to reduce the total memory operations and the number of the individual memories allowing operation without external memories. The architecture has been implemented on space grade and commercial FPGA Device. It achieves 136 MSamples/sec on space grade...
This paper presents a design method of reversible integer quaternionic paraunitary filter banks (Int-Q-PUFB) using the adder-based distributed arithmetic (DAΣ) for implementation multiplier block-lifting structure modules. The proposed quaternion multiplier (Q-MUL) and 8-channel Int-Q-PUFB processors are implemented on the FPGA Xilinx Zynq 7010. The total magnitude response of analysis-synthesis system...
In the last two decades the advancement in data communication techniques was significant, during the explosive growth of the Internet and demand for using multimedia has increased. Video and audio data streams require a bandwidth to be transferred in an uncompressed form. Several ways of compressing multimedia streams evolved. Image and video compression is one of the major components used in video...
Image compression and size reduction increases the number of images stored on a memory space and reduces bandwidth consumption while increasing transmission speed on a communication channel. Images can be compressed and decompressed using different methods and algorithms. With the vast increase of quality and size, dedicated processors with parallel processing blocks such as FPGAs are mainly targeted...
ExpEther is a virtualization technique that extends PCIe of a host CPU to Ethernet. Since all devices connected by ExpEther can be treated as if they were directly connected to the host, a multi-GPU system called GBU-BOX that connects a number of GPUs virtually to a host can be easily developed. However, the smaller bandwidth of Ethernet compared to PCIe often bottlenecks the system. An on-the-fly...
In order to reduce the pressure of data storage and transmission on satellite, researchers implemented a method of object region data extraction from remote sensing image in orbit. This method stores and downloads pixels of interesting region through interesting region labeling. But encoding data volume (EDV), hardware scale and real-time property (RTP) are difficult to be balanced. To solve this...
In recent years the growth in quantity, diversity and capability of Earth Observation (EO) satellites, has enabled increase's in the achievable payload data dimensionality and volume. However, the lack of equivalent advancement in downlink technology has resulted in the development of an onboard data bottleneck. This bottleneck must be alleviated in order for EO satellites to continue to efficiently...
The review of the main methods for lossless images compression that can be used in remote sensing tasks are given. The major advantages and disadvantages of image compression methods in terms of implementation on FPGA are shown. The recommendations are made for the use of compression techniques in the construction of onboard systems for remote sensing.
When dealing with the enormous remote sensing image, JPEG XR offers similar compression rate compared with JPEG2000, while consumes nearly the same resource as JPEG. Taking the limitation of power and computational resources onboard into consideration, FPGA-based hardware solution stands out with advantages of less resource requirement and higher speed. And the operation of JPEG XR is all in integer,...
In this paper the first low-latency architecture design and hardware implementation for structure-based inpainting to detect and complete isophotes in brain activity recording is presented. This novel mask-based compression and inpainting-based reconstruction methodology for correlated neural signals is especially important for the realization of implantable neural measurement systems (NMS) due to...
LZW algorithm is one of the most famous dictionary-based compression and decompression algorithms. The main contribution of this paper is to present a hardware LZW decompression algorithm and to implement it in an FPGA. The experimental results show that one proposed module on Virtex-7 family FPGA XC7VX485T-2 runs up to 2.16 times faster than sequential LZW decompression on a single CPU, where the...
The paper describes basic methods of data compression without loss and analyzes their advantages and disadvantages. There is a hardware implementation on FPGA of compression algorithm for stream processing of information. This algorithm can be used in applications related to telecommunications networks of distributed control systems.
In this paper we propose architecture to decrease the area utilization and improve the performance. To decrease the area utilization, a coherent 2D-DWT lifting based 9/7 wavelet is designed which also improves the performance. A coherent 2D-DWT method employed overlapped-stripe based scanning and stripe-based scanning for scanning the suitable inputs, so that temporal memory will get decreased. Usually...
Using the structure of FPGA and DSP to achieve real-time image processing system, Preprocessing the camera data with FPGA running speed and parallel processing ability and compressing transmission image by DSP. In the process of the image data of the dark, using the logarithm stretching algorithm, Increasing the image enhancement module, the image brightness uneven distribution becomes clear. Using...
In this era of Internet of Things, wherein every ‘thing’ is integrated within the existing internet architecture, it becomes quite necessary that embedded computing systems process quickly, occupy less area and consume low power. This would enable them to work quickly with real time data and have a large shelf life. As such there is a need for development of optimized algorithms and their efficient...
As the possibilities and the technology offered by the reconfigurable devices is improving constantly, reconfigurable computing is becoming a research area of interest for many researchers. Till date FPGA is the core device for reconfigurable computing. On the fly partial reconfiguration (PR) is an attractive feature of FPGA, which has opened up new directions for researchers. This feature allows...
Nowadays Field Programmable Gate Arrays (FPGAs) are increasingly considered in space applications as they are flexible and reprogrammable. They play an important role in geographical and weather forecasting processes. However, these devices are sensitive to the effects of radiation especially in modern de signs that deal with smaller CMOS structures. This paper discusses the various steps involved...
Efficient on-board lossless hyperspectral data compression reduces data volume in order to meet NASA and DoD limited downlink capabilities. The technique also improves signature extraction, object recognition and feature classification capabilities by providing exact reconstructed data on constrained downlink resources. At JPL a novel, adaptive and predictive technique for lossless compression of...
We present a hardware architecture of a heapsort algorithm, the sorting is employed in a subband coding block of a wavelet-based image coder termed Öktem image coder. Although this coder provides good image quality, the sorting is time consuming, and is application specific, as the sorting is repetitively used for different volume of data in the subband coding, thus a simple hardware implementation...
Fractal Image Compression (FIC) method provides a color image compression solution with an extremely high compression ratio, however it requires relative large amount of operations to complete codification. In this paper, we have developed an efficient approach for a fractal image compression applied to a color image, which utilizes a fractal coding on RGB to YCrCb color transformation and suitable...
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