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We present a miniaturized universal hardware module for acoustic pattern recognition in various types of multichannel sensor signals. The module implements configurable signal analysis (signal transforms, filter banks, statistical transforms) and a GMM-HMM recognizer. The main hardware components are a XC7A75T FPGA performing almost all the computations, a TMS320C6746 digital signal processor organizing...
The paper discusses the application of System on Chip devices for processing Megapixel video streams. The domain of image processing using high resolution images is very demanding in the scope of calculating power and frequently exploits special processing hardware. The progress of integration technology brings about SoC which are capable of meeting such processing demands. Characteristics of FPGA...
This paper presents the design and the implementation of real-time hardware enhancement digital image processing techniques for biomedical applications in a spatial domain on FPGA. It explains various enhancement techniques such as inverting image operation, brightness control, segmentation (threshold) and contrast stretching. A comparative study of all these techniques is carried out to find the...
The control algorithms and their software implementation play crucial role in real-time embedded systems reliability and safety. Field programmable gate arrays (FPGA) based hardware in the loop (HIL) is a relatively new technique used for development and testing of hard real-time complex systems. The system simulator implemented in FPGA provides real time reactions to control system actuations. The...
The exponential evolution of digital components and design practices places very high demands on engineering education. The traditional approach, based on gates and standard circuit blocks, in many institutions is being replaced by the introduction of HDL, in order to shorten the distance between the fundamentals and the state-of-the art application of today. We present here an approach that, while...
This paper mainly introduces the method for realizing storage control with a direct control of Hard Disk by using FPGA and DSP. And it uses a FIFO as a data cache so that the storage requrements for 80k Hz data sampling rate system can be satisfied.
To evaluate the total ionizing dose vulnerability of spaceborne signal processing platform, an accelerated radiation experiment is set up and on-orbit prediction method is proposed. For signal processing platform which consists of SRAM-based FPGA and DSP, function parameter and current variety are the two criterion of experiment. 60Co γ radial radiation experiment indicates that total dose is about...
The innovation and progress in the embedded technology have led to the advent of variety of architectures based on which a number of embedded computing platforms are available for implementing the design for digital signal processing applications. However the high performance requirements of the applications with shorter time-to-market force the designers to look for alternative platforms. A case...
Computerized interpretation of the electrocardiogram (ECG) is increasingly used to assist clinician experts to reduce times to reperfusion for patients suspected of ST-segment elevation myocardial infarction (STEMI). In this context, we have developed a system based on Field Programmable Gate Array (FPGA) for automatic detection of STEMI, using the MicroBlaze soft processor from Xilinx. More particularly,...
This work describes a 1 Gb/s digital communication system implemented on an FPGA-based platform to investigate mixed-signal calibration techniques of time-interleaved analog-to-digital converters (TI-ADCs). Design of multi-gigabit TI-ADCs is of great interest for next generation digital communication systems such as optical coherent networks. In these applications, mismatches of the sampling time,...
A software characterized radio framework, or Software Defined Radio SDR, is a radio correspondence framework where parts have ordinarily been executed in programming rather than equipment (e.g. blenders, channels, enhancers, modulators/demodulators, finders, and so forth.). Here the execution of our ongoing programming characterized radio framework is finished by field programmable door exhibits....
This paper presents advanced modulation technique for three-phase three-level ANPC inverter for drive applications. The Design of the converter allows actively balance the losses in the converter which results in higher power density, increase of reliability and lifetime of the converter. The control algorithm has to be able to secure the voltage control with proper capacitor voltage balancing as...
The seeker signal processor is a key device of a seeker. Based on the common characteristics extracted from seekers with different architectures, a general-purpose hardware scheme based on Field-Programmable Gate Array (FPGA) and Digital Signal Processor (DSP) is proposed. By taking full advantage of the FPGA and the DSP, the signal processor is equipped with the ability of high speed and real-time...
Finite impulse response (FIR) digital filters are extensively used due to their key role in various digital signal processing (DSP) applications. Several attempts have been made to develop hardware realization of FIR filters characterized by implementation complexity, precision and high speed. Field Programmable Gate Array is a reconfigurable realization of FIR filters. Field-programmable gate arrays...
This paper presents modulator with active voltage balancing control for three-phase four-level FLC converter based electric motor drive for applications supplied directly from a 6 kV ac-grid. It describes modulation algorithm of the drive with phase shifted PWM modulation with balancing voltage of flying capacitor by using P controllers in the closed loop. The proposed control is verified by experiments...
This paper presents the architecture of Arria 10, a high-density FPGA family built on the TSMC 20SOC process. The design of the device includes an embedded dual-core 1.5 GHz ARM A9 subsystem with peripherals, more than 1M logic elements (LEs) and 1.7M user flip-flops, and 64Mb of embedded memory organized into configurable memory blocks. The Arria 10 family is also the first mainstream FPGA family...
Using the structure of FPGA and DSP to achieve real-time image processing system, Preprocessing the camera data with FPGA running speed and parallel processing ability and compressing transmission image by DSP. In the process of the image data of the dark, using the logarithm stretching algorithm, Increasing the image enhancement module, the image brightness uneven distribution becomes clear. Using...
This paper describes the architecture and implementation, from both the standpoint of target applications as well as circuit design, of an FPGA DSP Block that can efficiently support both fixed and single precision (SP) floating-point (FP) arithmetic. Most contemporary FPGAs embed DSP blocks that provide simple multiply-add-based fixed-point arithmetic cores. Current FP arithmetic FPGA solutions make...
The radio channel is a critical but independent element affecting a wireless communication system. It is highly time-varying and exhibits behaviors such as path loss, shadowing, multi-path fading and Doppler spread. In this paper, we discuss the design and implementation of a real-time Multi-Terminal Channel Emulator on an SDR (Software Defined Radio) platform for providing controlled variability...
Power consumption is one of the major concerns while mapping designs on FPGAs. Dynamic power dissipation in FPGAs is a strong function of the switching activity of the nodes and the charging and discharging capacitances associated with the critical path. This paper focuses on reducing the power dissipation in bit-parallel unfolded CORDIC structures by modeling the switching activity and the charging/discharging...
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